Split-Voltage EEPROM Row Control for Low-Stress Programming
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Solution Overview
Problem
EEPROM memories face reliability issues due to high programming voltages, leading to transistor breakdown and premature aging, particularly in split voltage architectures, which complicate row control circuits in terms of current consumption and transistor count.
Innovation Solution
A non-volatile memory device with a split voltage architecture that uses a first row control circuit with an exclusive NOR logic gate and inverter connected downstream of the latch device to manage voltage transitions without altering the latch device's output state, and a second row control circuit with a NAND gate and inverter to control selection transistors, along with a compact SR latch flip-flop for stable operation at low voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high voltage (9-20V) is used for programming EEPROM memories, then programming operation is achieved, but transistor reliability deteriorates due to breakdown and premature aging
Solution Approach 1:
The high programming voltage is segmented into two separate voltage signals: a first voltage signal applied to the control gate and a second voltage signal applied to the source. This segmentation allows the high voltage stress to be distributed across different transistor regions rather than concentrated at the gate oxide, thereby improving transistor reliability while maintaining programming functionality.
2Reliability
If split voltage architecture is used to reduce transistor stress, then reliability improves, but row control circuit complexity increases
Solution Approach 1:
The row control circuit merges the control of the first and second voltage signals into a single control element (inverter) that receives one control signal. This merging approach simplifies the row control circuit by reducing the number of control elements and transistors required, while still maintaining the split voltage architecture benefits for transistor reliability.
3Ease of operation
If conventional row control is used in split voltage architecture, then two different signals are decoded per physical row, but current consumption and transistor count increase
Solution Approach 1:
The single control element (inverter) performs multiple functions: it controls both the first voltage signal for state transistor gates and the second voltage signal for source voltage. This multi-functionality reduces the number of control elements required, thereby reducing current consumption and transistor count while maintaining full row control capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces current consumption, minimizes transistor stress, and enhances reliability by stabilizing voltage transitions, preventing latch device collapse and incorrect switching, while allowing operation at low voltages.
Implementation Method 1
The programming or the erasing of a floating-gate transistor includes the injection or the extraction of the electric charges in the gate of the transistor by tunnel effect (referred to in the art as the 'Fowler-Nordheim' effect) via a high voltage.
Data Source
AI summary
A nonvolatile memory device has a “split-voltage” architecture and includes columns of memory words formed on each row by groups of memory cells. All state transistors for memory cells of a memory word are gate controlled by a control element. All control elements of a same row are controlled by a first control signal generated by a first row control circuit in response to a set-reset (SR) latch output signal output for a selected row. In order to write a piece of data in a memory word, the first row control circuit confers onto the first control signal an erasing voltage corresponding to a first logic state of the first control signal and then a programming voltage corresponding to a second logic state of the first control signal without modifying, between erasing and programming the memory word, the state of the latch output signal for the selected row.