Split-Voltage Memory Array for Stable Vector-Matrix Multiplication
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current non-volatile memory technologies, such as flash memory, face limitations in power consumption and operational speed, leading to high memory latency that can hinder microprocessor performance and communication protocols, particularly in applications requiring fast data access and processing like machine learning algorithms.
Innovation Solution
The implementation of a split-voltage approach in memory devices, specifically in resistive switching memories like CBRAM and ReRAM, allows for a higher number of stable conductance states by applying sub-voltages to memory cell layers, enabling more accurate and repeatable vector-matrix multiplication operations, which is crucial for machine learning and other computational tasks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If flash memory is used for non-volatile storage, then data retention is improved, but power consumption increases and operation speed decreases
Solution Approach 1:
The patent changes the electrical parameters (voltage levels, conductance states) of the memory cells to enable vector-matrix multiplication operations. By programming memory cells to specific conductance states and applying controlled voltage signals, the system performs computational operations directly in memory, reducing power consumption compared to traditional flash memory operations while maintaining data retention capabilities.
Solution Approach 2:
The patent replaces traditional mechanical/electronic computation systems with a memory-based computational approach. Instead of using separate processors to perform calculations, the system uses the memory array itself to perform vector-matrix multiplication through electrical conductance relationships, thereby reducing overall system power consumption.
2Stability of the object's composition
If flash memory is used for non-volatile storage, then data retention is improved, but operation speed decreases
Solution Approach 1:
The patent merges the functions of memory storage and computational processing into a single integrated system. By performing vector-matrix multiplication operations directly within the memory array, the system eliminates the need for data transfer between memory and processor, thereby significantly improving operation speed while maintaining the non-volatile data retention characteristics of flash memory.
Solution Approach 2:
The patent replaces traditional sequential memory access and external processing with parallel in-memory computation. The memory array simultaneously performs multiple multiplication and addition operations through electrical conductance relationships, achieving high-speed computational operations while maintaining data retention.
3Speed
If memory latency is reduced for microprocessor performance, then processing speed is improved, but communication protocol complexity increases
Solution Approach 1:
The patent extracts the computational function from the traditional processor-memory communication protocol. By performing vector-matrix multiplication operations directly within the memory array, the system eliminates the need for complex communication protocols between the microprocessor and memory, as the computational results are generated directly at the memory location without requiring extensive data transfer and processing cycles.
4Measurement precision
If the number of conductance states is increased for better computational accuracy, then vector-matrix multiplication precision is improved, but memory cell stability requirements increase
Solution Approach 1:
The patent uses parameter changes in a controlled manner to achieve multiple conductance states. By applying different voltage levels and programming sequences, the system programs memory cells to specific conductance states corresponding to matrix weights. The split-voltage approach divides the voltage range into sub-ranges, allowing precise control of conductance states while maintaining stability through controlled programming operations rather than requiring inherently unstable high-density conductance states.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the numerical accuracy and stability of memory-based vector-matrix multiplication, accommodating a larger number of conductance levels without requiring significant changes in memory cell conductance, thus improving computational efficiency and reducing latency.
Implementation Method 1
resistive switching memories like CBRAM and ReRAM
Data Source
AI summary
A memory device includes a memory array arranged in rows and columns; memory cell layers at each row and column intersection, where each memory cell layer is configured to be set to a predetermined conductance state; a row control circuit that is configured to apply voltages to the rows by applying sub-voltages on each row, where each sub-voltage corresponds to a different memory cell layer, and where each sub-voltage is proportional to the voltage on the corresponding row; and a sensing circuit that is configured to determine a column current flowing through a selected column in response to the application of the voltages to the rows, where the column current is a sum of currents through each memory cell layer that corresponds to the selected column.