Split Word Line Driver Circuit Layout for Memory Integration Density

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Solution Overview

Problem

Conventional semiconductor memory devices with sub-word line driver structures face challenges in minimizing layout area and achieving high integration density due to the presence of sub-wordline driver arrays between memory arrays, which affects operating efficiency and integration level.

Innovation Solution

The semiconductor memory device incorporates a layout pattern with sub-word line driver circuits arranged in columns, where each column group consists of four sub-word line driver circuits, with adjacent columns forming a group to drive even or odd sub-word lines, optimizing layout by sharing signal nodes and reducing space occupancy.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If sub-word line driver circuits are arranged in conventional layouts between memory arrays, then the memory device can operate with hierarchical word line structures, but the layout area increases and integration density decreases

Engineering Contradiction:

Improveoperating efficiencyVSAvoidlayout area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

Adjacent sub-word line driver circuits are merged into shared blocks where multiple driver circuits share common active regions, gate structures, and interconnect resources. This consolidation reduces the total layout area while maintaining the functional capability to drive multiple sub-word lines independently.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The sub-word line driver blocks are designed with multi-functional transistor structures that can serve multiple driving functions. The same physical driver block structure is used to drive different sub-word lines through selective activation, reducing the need for separate dedicated driver structures for each sub-word line.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Quantity of substance

If sub-word line driver circuits are integrated densely to increase integration density, then layout area is minimized, but the complexity of signal node sharing and layout optimization increases

Engineering Contradiction:

Improveintegration densityVSAvoidlayout complexity

Core Design Contradiction:

Quantity of substanceVSDevice complexity

Solution Approach 1:

The memory device is divided into multiple memory blocks, each associated with dedicated sub-word line driver blocks. This segmentation allows each driver block to be independently optimized and laid out in a standardized manner, reducing overall layout complexity while achieving high integration density through systematic repetition of the segmented units.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Multiple levels of hierarchy are implemented where sub-word line driver circuits are nested within memory blocks, which are in turn nested within larger memory array structures. This nested organization allows for systematic layout planning at different scales, reducing the complexity of signal routing and node sharing.

Inventive Principle:

Principle #7Nested doll (Nesting)

Data Source

PatentUS7729195B2Semiconductor memory device having split word line driver circuit with layout patterns that provide increased integration density

Publication Date: 2010.06.01 SAMSUNG ELECTRONICS CO LTD

AI summary

Semiconductor memory devices having hierarchical word line structures are provided. A block of sub-word line driver circuits (SWDB) are disposed between a first block of memory and a second block of memory. A SWDB includes a plurality of sub-wordline driver (SWD) circuits arranged in a plurality of SWD columns each having four SWD circuits extending in a first direction between the first and second blocks of memory. Two adjacent SWD columns include a SWD group for driving a plurality of sub-word lines extending from the SWD group along the first direction into the first and second blocks of memory.