Split Word Line Memory Layout for Lower Capacitive Loading
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Solution Overview
Problem
Existing memory devices face challenges in reducing capacitive loading, which affects operating speed and power consumption, particularly in three-dimensional memory arrays.
Innovation Solution
Implementing split word lines and switches to decouple local lines from global lines selectively, reducing capacitive loading by configuring subsets of memory cells to be accessed independently, and sharing drivers to minimize processing complexity and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If memory devices use traditional single word line architecture, then device complexity is low, but capacitive loading increases affecting operating speed and power consumption
Solution Approach 1:
The patent divides a single word line into multiple segmented word lines (first word line and second word line), where each segment is independently controlled. This segmentation reduces the capacitive loading on each individual word line segment, thereby improving operating speed and reducing power consumption while maintaining manageable device complexity through systematic organization
2Quantity of substance
If memory devices increase storage density, then capacity increases, but capacitive loading increases affecting performance
Solution Approach 1:
By segmenting the word line into multiple independent segments, the patent enables selective activation of only the necessary word line segments for accessing specific memory cells. This reduces the total capacitive loading that must be charged and discharged during operations, thereby reducing power consumption while supporting higher storage density through more efficient memory cell organization
3Use of energy by stationary object
If memory devices use segmented word lines and switches, then capacitive loading is reduced improving speed, but device complexity increases
Solution Approach 1:
The patent implements segmentation of word lines with associated switches for selective coupling, but organizes these segments in a systematic manner where each segment serves specific memory cell subsets. This structured segmentation reduces power consumption through selective activation while keeping device complexity manageable through regular patterning and systematic control signal generation
Data Source
AI summary
Systems and methods disclosed herein are related to a memory system. In one aspect, the memory system includes a first set of memory cells including a first string of memory cells and a second string of memory cells; and a first switch including: a first electrode connected to first electrodes of the first string of memory cells and first electrodes of the second string of memory cells, and a second electrode connected to a first global bit line, wherein gate electrodes of the first string of memory cells are connected to a first word line and gate electrodes of the second string of memory cells are connected to a second word line.