Splitter-Driven Push-Pull Power Amplifier for Lower Ripple Loss
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Solution Overview
Problem
Existing power amplifiers face issues such as high power consumption due to high local oscillator current, increased off-chip component costs from additional filters, and efficiency loss due to IR drops and DC-DC buck ripple, particularly in open-drain and transformer-based push-pull PAs.
Innovation Solution
A splitter-based push-pull PA design using P-type and N-type transistors with a splitter to receive a common-mode input pair, providing differential output pairs to transistor gates, eliminating the need for additional filters and reducing DC current flow to improve efficiency and reduce ripple.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If open-drain PA is used, then power amplification is achieved, but high LO current is required increasing power consumption
Solution Approach 1:
The PA is divided into two independent push-pull branches (first and second branches), each handling different signal phases. This segmentation allows each branch to operate with lower individual LO current requirements while collectively achieving the desired power amplification output.
Solution Approach 2:
The patent combines the outputs of two push-pull branches to achieve the final power amplification. By merging the signal paths and using a combined output structure, the system achieves high power amplification without requiring high LO current in a single path, thus reducing overall power consumption.
2Power
If open-drain PA is used, then power amplification is achieved, but additional BPFs or notch filters are required increasing off-chip component cost
Solution Approach 1:
The patent extracts and eliminates the need for external BPFs and notch filters by integrating the filtering function into the push-pull branch architecture itself. The differential signal generation and balanced output structure inherently suppress harmonics and spurs, removing the requirement for additional off-chip filtering components.
Solution Approach 2:
The push-pull branch structure serves multiple functions simultaneously: it provides power amplification, signal differential conversion, and harmonic suppression. This multi-functionality integrates what would traditionally require separate components (amplifier and filters) into a single architectural solution, reducing off-chip component requirements.
3Power
If output balun with center tap is used, then power amplification is achieved, but large DC current causes IR drop impacting PA efficiency
Solution Approach 1:
Instead of using a traditional output balun with center tap that requires large DC current, the patent inverts the approach by using the push-pull branch architecture to directly generate differential signals. This eliminates the need for the conventional balun structure and its associated DC current path, thereby eliminating the IR drop problem and improving PA efficiency.
4Reliability
If transformer-based push-pull PA is used, then open-drain PA disadvantages are overcome, but large DC-DC buck ripple problem occurs
Solution Approach 1:
The patent introduces an intermediate differential signal generation stage using the splitter and push-pull branches before the final power amplification. This intermediary structure transforms the signal in a way that eliminates the direct coupling between the DC-DC converter and the PA output, thereby suppressing the transmission of buck ripple while maintaining the advantages of the push-pull architecture.
Data Source
AI summary
A push-pull power amplifier (PA) includes a pair of P-type transistors, a pair of N-type transistors, and a splitter, wherein source terminals of the pair of P-type transistors are coupled to a first reference voltage, source terminals of the pair of N-type transistors are coupled to a second reference voltage, and drain terminals of the pair of P-type transistors and drain terminals of the pair of N-type transistors are coupled to an output port of the push-pull PA. The splitter is arranged to receive a common-mode input pair, and provide two differential output pairs to the pair of P-type transistors and the pair of N-type transistors, wherein one of the two differential output pairs is provided to gate terminals of the pair of P-type transistors, and the other of the two differential output pairs is provided to gate terminals of the pair of N-type transistors.