Splitting Circuitry for Thread Set Allocation in SIMT Data Processing
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Solution Overview
Problem
In Single Instruction Multiple Thread (SIMT) systems, dividing threads into sets for parallel execution can lead to unnecessary memory access requests due to misalignment with storage boundaries, causing inefficiencies in data processing.
Innovation Solution
A data processing apparatus and method that divides threads into sets based on storage boundaries to minimize memory access requests, using splitting circuitry to allocate threads and generate control signals for efficient access to data values stored in groups defined by storage boundaries.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If threads are divided into sets for parallel execution, then processing throughput is improved, but the number of memory access requests increases due to misalignment with storage boundaries
Solution Approach 1:
The patent divides n threads into multiple sets of threads, where each set contains fewer than n threads. The splitting circuitry allocates threads to sets based on storage boundaries, ensuring that threads accessing data from the same storage boundary are grouped together. This segmentation allows parallel processing while minimizing redundant memory access requests, as each set can be serviced by a single aligned access request.
2Productivity
If threads are divided into sets without considering storage boundaries, then parallel execution is improved, but redundant cache line access occurs
Solution Approach 1:
The splitting circuitry performs preliminary allocation of threads to sets based on storage boundaries before memory access requests are generated. By determining the storage boundary alignment in advance, the system can group threads that will access the same cache line together, ensuring that each cache line is accessed only once even when multiple threads in a set request data from the same boundary-aligned storage location.
Data Source
AI summary
A data processing apparatus 10 for executing an access instruction for n threads in order to access data values for the n threads includes storage circuitry 100 that stores data values associated with the n threads in groups defined by storage boundaries. The data processing apparatus also includes processing circuitry 80 that processes the access instruction for a set of threads at a time (where each set of threads comprises fewer than n threads) and splitting circuitry 110, responsive to the access instruction, to divide the n threads into multiple sets of threads, and to generate at least one control signal identifying the multiple sets. For each of the sets, the processing circuitry responds to the at least one control signal by issuing at least one access request to the storage circuitry in order to access the data values for that set. The splitting circuitry determines into which set each of the n threads is allocated having regards to the storage boundaries.