Scratch-Pad Memory Data Managing Unit for Processor Bottleneck
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current processor systems face reduced data processing ability due to inefficient data handling, particularly with cache memory, which leads to increased memory size and energy consumption, and a higher likelihood of cache misses, ultimately limiting data processing rates.
Innovation Solution
A processor design incorporating a data managing unit that reads data from an external memory, converts it into batch data, and stores it in a scratch-pad memory (SPM), utilizing both a data cache and a direct route to the external memory for efficient data preparation and processing, allowing separate data preparation and processing operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If cache memory is used to store data between processor core and external memory, then data access speed is improved, but memory size and energy consumption increase due to additional tag check circuitry
Solution Approach 1:
The patent extracts the tag check circuitry from the memory system by using a scratch-pad memory with unique address space instead of cache memory. This removes the unnecessary hardware components while maintaining fast data access capability through direct addressing.
Solution Approach 2:
The scratch-pad memory uses simple addressable storage without complex tag checking mechanisms. It accepts that data may need to be reloaded from external memory but eliminates the overhead of cache management hardware, achieving a simpler, more energy-efficient solution.
2Adaptability or versatility
If processor core manages both reading data and processing data, then integration is improved, but data processing ability substantially decreases due to data reading rate being lower than processor operation rate
Solution Approach 1:
The data managing unit performs preliminary action by reading data from external memory and converting it to batch data before the processor core needs it. This prepares data in advance so the processor core can immediately process without waiting for data retrieval, eliminating the bottleneck.
Solution Approach 2:
The patent segments the data handling function from the processing function by introducing a separate data managing unit. This unit handles data reading and conversion while the processor core focuses on processing, allowing parallel operation and improving overall throughput.
3Quantity of substance
If data is read from external memory at lower rate than processor operation rate, then memory bandwidth is reduced, but data processing ability of processor substantially decreases
Solution Approach 1:
The data managing unit reads data from external memory in advance and converts it to batch data format before the processor core requires it. This preliminary data preparation ensures that when the processor needs data, it is already available in the required format, eliminating the bottleneck caused by slow external memory access.
Data Source
AI summary
A processor and a memory controlling method. The processor enables a Scratch-Pad Memory (SPM) to prepare data that a processor core intends to process, using a data management unit including a data cache, thereby increasing a data processing rate.