SPMI Bus Hang Correction via Secondary Master Timer Arbitration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In systems using the System Power Management Interface (SPMI) bus, hangs can occur when a winning master fails to assert a clock signal, leading to potential performance degradation or latency due to the need for bus restarts.
Innovation Solution
Secondary master devices utilize timers to determine if the winning master has asserted a clock signal within a predefined time; if not, they assume ownership of the bus and assert a clock signal, maintaining bus ownership and preventing restarts by using Master Identification (MID) values to set timer values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a winning master fails to assert a clock signal, then bus operations halt and require restart, but this causes performance degradation and latency
Solution Approach 1:
Secondary masters are pre-configured with timer mechanisms and priority levels before bus operations begin. When arbitration occurs, secondary masters immediately start their timers and prepare to take over if the winning master fails to assert a clock signal within the predetermined time period, ensuring continuous bus operation without restarts
Solution Approach 2:
The system implements a feedback mechanism where secondary masters continuously monitor the bus for clock signals from the winning master. If no clock signal is detected within the timer period, the secondary master with the highest priority among those whose timers expired takes over the bus, providing automatic correction of hung conditions
2Reliability
If secondary masters monitor for hang conditions using timers, then bus ownership can be maintained, but this increases system complexity
Solution Approach 1:
The hang detection and recovery function is segmented into independent timer modules assigned to each secondary master. Each timer operates autonomously with its own predetermined time period based on the secondary master's priority level, allowing modular implementation without requiring complex centralized control logic
Solution Approach 2:
The system uses parameter changes in the form of priority levels (first, second, third priorities) assigned to secondary masters. These priority levels directly determine the predetermined time periods for their respective timers, with higher priority masters having shorter time periods. This parameter-based approach simplifies the control logic compared to complex arbitration algorithms
Data Source
AI summary
The systems and methods for hang correction in a power management interface bus cause secondary master devices associated with the power management interface bus to utilize timers to determine if a master that won arbitration has asserted a clock signal within a predefined amount of time. If a timer for a secondary master device expires without a clock signal being asserted by the winning master, the secondary master will assume ownership of the bus and assert a clock signal. Priorities between secondary masters are created by using a master identification (MID) value assigned during bus enumeration to determine a timer value. By allowing the secondary masters to assume ownership after expiration of respective timers, bus ownership is maintained in the event that a winning master hangs and does not assert ownership.