SPMI Bus Level Translator With One-Shot Switching for Fast Edges
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Solution Overview
Problem
Current level translators for SPMI buses face challenges with high leakage current and slow signal rise and fall times, which are not sufficient to meet the performance requirements of mobile devices operating in different voltage domains.
Innovation Solution
A level translator circuit design incorporating one-shot circuits and switches that reduce leakage current by controlling the switches during signal transitions, allowing for fast and accurate signal translation between 1.2V and 1.8V voltage domains, utilizing transistors and resistors to manage voltage levels and enable efficient communication across different voltage domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional level translators are used for SPMI bus, then voltage level translation between 1.2V and 1.8V domains is achieved, but leakage current is high and signal rise/fall times are slow
Solution Approach 1:
The patent applies dynamics by making the pull-up switches active only during signal transitions rather than continuously conductive. The control logic detects edge transitions and temporarily enables the appropriate pull-up switch (MP1/MP2 for rising edges, MN1/MN2 for falling edges), allowing fast signal transitions when needed while keeping switches non-conductive during stable states to minimize leakage current.
Solution Approach 2:
The patent implements periodic action through one-shot circuits that generate temporary enable pulses synchronized with signal transitions. When a transition is detected, the one-shot circuit activates the pull-up switch for a fixed duration sufficient to complete the voltage transition, then automatically disables it. This periodic activation pattern achieves fast rise/fall times during transitions while maintaining low leakage during stable periods.
2Speed
If level translator circuit is designed for fast signal transitions, then signal rise and fall times are reduced, but power consumption increases due to continuous switching activity
Solution Approach 1:
The patent applies preliminary action by detecting signal transitions and preemptively enabling the appropriate pull-up switch before the voltage transition completes. The control logic monitors input signals and activates the switching elements in advance of the actual voltage change, ensuring fast transitions are initiated immediately when needed, rather than waiting for voltage levels to naturally change.
Solution Approach 2:
The patent implements feedback through control logic that continuously monitors the states of input and output signals. Based on this feedback, the control logic dynamically determines when transitions are occurring and selectively enables/disables pull-up switches. This feedback mechanism ensures switching elements are activated only when transitions are detected, optimizing the balance between transition speed and power consumption by avoiding unnecessary continuous switching.
Data Source
AI summary
A bi-directional level translator with fast rise and fall times and low current leakage is suitable for use with devices connected using a SPMI bus. The level translator passes signals between first and second voltage domains that operate at different voltage levels. The level translator has a first terminal that receives a first signal A from the first voltage domain and outputs a second signal B to the second voltage domain. A second terminal receives the second signal B and outputs the first signal A. A first switch is located between the first voltage source and the first terminal and a second switch is located between the second voltage source and the second terminal. The first and second switches are operable to reduce current leakage of the level translator.