Spot-Solderable Semiconductor Leads With Selective Surface Masks
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Solution Overview
Problem
The challenge in semiconductor device packaging is to reduce lead resistance and spacing while preventing solder bridging, which is exacerbated by the fragility of thin leadframes and the need for high current-carrying metal leads in densely packed devices, leading to increased thermal dissipation and miniaturization demands.
Innovation Solution
The solution involves using full-thickness metal leads with selective surface treatments to render adjacent portions non-wettable by solder, achieved through polymer-based masks, surface energy modification, or insulator-filled grooves, ensuring safe lead spacing and preventing solder bridging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If thin reduced-thickness leadframes (half-etched leadframes) are used to achieve tighter lead spacing, then lead spacing is reduced, but the leadframes become too fragile to handle
Solution Approach 1:
The patent applies different thicknesses of metal leads in different locations: full metal thickness in areas requiring strength (power leads, heat dissipation areas) and half-etched portions in areas where narrow spacing is needed. This local differentiation resolves the contradiction by providing both structural integrity where needed and compact spacing where required.
2Quantity of substance
If full metal thickness leads are used for high current-carrying capacity, then current-carrying ability is improved, but lead spacing increases and device miniaturization is hindered
Solution Approach 1:
The patent uses full metal thickness for power leads that require high current-carrying capacity while using half-etched portions for signal leads where narrow spacing is sufficient. This spatial differentiation of metal thickness allows the device to achieve both high current capability and compact dimensions.
3Length of moving object
If leads are closely spaced for device miniaturization, then device size is reduced, but the risk of solder bridging increases
Solution Approach 1:
The patent applies a polymer-based mask or surface energy modification to lead portions before the soldering process. This preliminary treatment creates non-wettable surfaces that prevent solder from bridging between closely spaced leads, allowing miniaturization without compromising reliability.
4Shape
If half-etched portions are covered by molding compound to achieve coplanar surfaces, then surface flatness is improved, but the exposed area for solder attachment is reduced
Solution Approach 1:
The patent selectively positions half-etched portions and full metal portions to optimize both surface flatness and solder attachment area. The molding compound covers half-etched portions to achieve coplanarity, while full metal portions are strategically placed to provide adequate solder attachment area, resolving the contradiction through spatial optimization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces lead resistance, minimizes solder bridging risks, and allows for tighter lead spacing, enhancing the frequency and efficiency of DC-DC converters by maintaining structural integrity and preventing electrical shorts.
Implementation Method 1
selective surface treatments to render adjacent portions non-wettable by solder, achieved through polymer-based masks, surface energy modification
Implementation Method 2
insulator-filled grooves, ensuring safe lead spacing and preventing solder bridging
Data Source
AI summary
A semiconductor device that has at least one semiconductor chip attached to a leadframe made of sheet metal of unencumbered full thickness. The leadframe has leads of a first subset that alternate with leads of a second subset. The leads of the first and second subsets have elongated straight lead portions that are parallel to each other in a planar array. A cover layer of insulating material is located over portions of un-encapsulated lead surfaces. The portions of the leads of the first and second subsets that don't have the cover layer have a metallurgical configuration that creates an affinity for solder wetting.