Spread Clock Domain Data Transfer FIFO Controller
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Solution Overview
Problem
Serializer/deserializer communication systems face electromagnetic interference (EMI) issues due to the concentration of energy at a single frequency in clock signals, which can affect nearby components.
Innovation Solution
A system that converts data from a non-spread clock domain to a spread clock domain using a FIFO memory and a spread-clock generator, which modulates the clock signal to distribute energy across a broader frequency range, reducing EMI by preventing data overflow or underflow through dynamic frequency adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a constant frequency clock signal is used for data transmission, then timing information is provided accurately for receiving serial data, but electromagnetic interference (EMI) is generated due to energy concentration at a single frequency
Solution Approach 1:
The patent applies parameter changes by modulating the clock signal frequency according to the data being transmitted. Instead of using a constant frequency clock signal, the system varies the clock frequency dynamically, causing the energy to be distributed across multiple frequencies rather than concentrated at a single frequency, thereby reducing EMI while maintaining accurate timing information for data reception
Solution Approach 2:
The patent implements dynamics by making the clock signal adaptive and variable rather than static. The clock frequency is dynamically adjusted based on the data pattern being transmitted, allowing the system to maintain synchronization accuracy while spreading energy across different frequencies to minimize electromagnetic interference
2Object-generated harmful factors
If the clock signal frequency is spread across multiple frequencies, then electromagnetic interference is reduced, but data overflow or underflow may occur in the FIFO memory
Solution Approach 1:
The patent employs feedback mechanisms through write and read pointers that continuously monitor the FIFO memory status. The write pointer tracks data written to the FIFO while the read pointer tracks data read from it, providing real-time feedback on the memory fill level. This feedback allows the system to detect potential overflow or underflow conditions and adjust the spread clock frequency accordingly to prevent data loss
Solution Approach 2:
The patent applies preliminary action by using the write and read pointers to predict and prevent potential data overflow or underflow conditions before they occur. The pointers continuously monitor the FIFO status in advance, allowing the system to take corrective frequency adjustments proactively rather than reactively, ensuring data integrity while maintaining spread spectrum operation
Data Source
AI summary
An apparatus for transferring data in a non-spread domain to a spread domain. The apparatus comprises a first-in-first-out (FIFO) memory; a write pointer generator adapted to generate a write pointer for writing data into the FIFO memory in response to a non-spread clock signal; a spread-clock generator adapted to generate a spread clock signal based on the non-spread clock signal; a read pointer generator adapted to generate a read pointer for reading data from the FIFO memory in response to the spread clock signal; and a controller adapted to control the spread-clock generator in response to the read and write pointers indicating predetermined potential data overflow or underflow of the FIFO memory.