Spread Spectrum Clock Sequencing for EMI Reduction
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Solution Overview
Problem
The increasing performance requirements of electronic devices lead to higher electromagnetic interference (EMI) due to increased current consumption and frequency usage, necessitating a method to reduce EMI emissions effectively.
Innovation Solution
A spread spectrum clock generation device that includes a clock delay circuit generating multiple delay clock signals with varying phase delays, an output circuit selecting and sequencing these signals to produce an output clock signal with a wider frequency spectrum and longer cycle than the reference clock signal, and a phase connection circuit identifying and compensating for phase delays exceeding 2π to minimize EMI.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the frequency of the clock signal is increased to meet high performance specifications, then the processing speed and performance of electronic devices are improved, but the electromagnetic interference emission amount increases
Solution Approach 1:
The patent segments the concentrated clock signal frequency into multiple distributed frequency components through spread spectrum clocking. By modulating the clock signal to distribute its energy across a wider frequency range, the peak emission at any single frequency is reduced while maintaining the overall processing performance.
Solution Approach 2:
The patent changes the frequency distribution parameters of the clock signal from a concentrated single frequency to a distributed spectrum. By adjusting the spread spectrum modulation parameters, the clock signal's energy is redistributed across multiple frequencies, reducing electromagnetic interference while preserving timing performance.
2Productivity
If the current consumption is increased to meet high performance requirements, then the processing capability of electronic devices is improved, but the electromagnetic interference emission amount increases
Solution Approach 1:
The patent segments the high-current clock signal's electromagnetic energy into distributed frequency components. By using spread spectrum modulation, the concentrated energy that causes EMI is divided into multiple lower-level frequency components, reducing peak emissions while maintaining the processing capability enabled by the high current.
Solution Approach 2:
The patent converts the harmful concentrated electromagnetic energy into a beneficial distributed spectrum. The spread spectrum technique transforms the EMI problem by deliberately spreading the energy across frequencies, which reduces peak emissions and can even improve signal robustness and timing performance.
3Speed
If the bandwidth of the clock signal frequency is concentrated to improve processing speed, then the clock signal effectiveness is improved, but the electromagnetic interference emission amount increases
Solution Approach 1:
The patent segments the concentrated clock signal bandwidth into distributed frequency components through spread spectrum modulation. This segmentation reduces the peak spectral density that causes EMI while maintaining the overall bandwidth and timing effectiveness needed for high-speed processing.
Solution Approach 2:
The patent introduces dynamic frequency modulation to the clock signal, making the frequency content time-varying through spread spectrum techniques. This dynamic approach distributes the energy in time and frequency domains, reducing instantaneous EMI while preserving the average processing performance.
Data Source
AI summary
A device includes a clock delay circuit configured to receive a reference clock signal and generate N delay clock signals, where N is a natural number greater than or equal to 2, by using the reference clock signal, and an output circuit configured to receive the N delay clock signals and output at least a portion of the delay clock signals from among the N delay clock signals as an output signal, wherein a phase delay of a delay clock signal that is output later in time from among the at least the portion of the delay clock signals is greater than or equal to a phase delay of a delay clock signal that is output earlier in time, and wherein a cycle of the output clock signal is longer than or equal to a cycle of the reference clock signal.