Spread Spectrum Clock Generator With Staged Dividers for Low Jitter
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Solution Overview
Problem
Conventional spread spectrum clock generators face challenges in reducing jitter and achieving high frequency offset ratios due to limitations in the number of signals output from a voltage-controlled oscillator (VCO), which complicates circuit logic and operation, and is restricted by the need for non-integer division ratios and phase delays.
Innovation Solution
A semiconductor device with a frequency dividing unit and phase offset unit that generates feedback signals with predetermined phase differences, utilizing a series of frequency dividers and a selector to output a plurality of signals with different phase differences, allowing for higher frequency operation and reduced jitter by increasing the number of signals from the VCO.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of signals output from VCO is increased to reduce jitter and achieve higher frequency offset ratios, then the spread spectrum clock signal quality is improved, but the circuit logic becomes more complex and operation becomes more difficult
Solution Approach 1:
The frequency dividing unit is divided into multiple frequency dividers (first frequency divider, second frequency divider) that operate in series. Each frequency divider handles a portion of the frequency division task, allowing the system to achieve high frequency offset ratios and reduced jitter without requiring a single complex division stage. This segmentation enables independent optimization of each divider stage.
Solution Approach 2:
A selector is introduced as an intermediary component between the frequency dividers and the feedback path. The selector chooses between different feedback signals based on operating conditions, enabling flexible control over the number of VCO signals used while maintaining simple circuit logic. This intermediary allows the system to adapt between different modes without reconfiguring the entire circuit.
2Measurement precision
If non-integer division ratios are used to achieve precise phase delays, then the phase accuracy is improved, but the circuit operation becomes more complex and difficult to implement
Solution Approach 1:
The overall non-integer division ratio is segmented into multiple integer division stages. The first frequency divider performs one integer division, and the second frequency divider performs another integer division. The combination of these staged integer divisions achieves the equivalent of a non-integer division ratio while maintaining simple integer arithmetic in each stage, avoiding the complexity of implementing direct non-integer division.
Solution Approach 2:
The system uses periodic selection of feedback signals through the selector, which operates at different periods depending on the desired frequency offset ratio. This periodic action allows the system to achieve precise phase control by selecting appropriate feedback signals at regular intervals, rather than requiring continuous non-integer division operations.
Data Source
AI summary
A semiconductor device, a spread spectrum clock generator and method thereof are provided. The example semiconductor device may include a frequency dividing unit receiving an output signal, generating a first feedback signal and a second feedback signal by dividing a frequency of the received output signal, and a phase offset unit outputting the output signal having a predetermined or desired phase difference with a reference signal in response to the second feedback signal, wherein the second feedback signal having a higher frequency than the first feedback signal. The example spread spectrum clock generator may include a plurality of frequency dividers which are connected in series and a selector selecting and outputting one of a plurality of output signals, each of the plurality of output signals having a different phase difference with respect to a reference signal, in response to at least one output from one or more of the plurality of frequency dividers. The example method may include receiving a reference signal with a first frequency, generating a feedback signal having a second frequency, the second frequency higher than the first frequency and outputting at least one of a sequentially selected set of output signals in response to the generated feedback signal.