Spread Spectrum Reference Clock with Phase Delta-Sigma Remapping
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Solution Overview
Problem
Traditional Spread Spectrum Clock Generators (SSCGs) face performance degradation at lower spectrum amplitudes due to limited resolution of delta-sigma (Δ-Σ) modulators, especially when trying to reduce Electromagnetic Interference (EMI) in PC motherboards, and increasing frequency or resolution is limited by power consumption and maximum operation frequency.
Innovation Solution
A method and apparatus that improve the resolution of the Fraction N counter by 2*K times using a two-stage post phase synchronization technique and remapping of Δ-Σ quantization results, allowing the minimum swing step of the frequency divider to be reduced from 2 to 1, and introducing an offset value of ±½, which enhances timing accuracy and reduces design complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the operation frequency is increased to improve timing accuracy, then the resolution of the frequency divider improves, but the power consumption increases and the maximum operation frequency is exceeded
Solution Approach 1:
The patent segments the frequency division process into two stages: a first frequency divider operating at a lower frequency to provide coarse division, and a second frequency divider operating at a higher frequency to provide fine division. This segmentation allows the system to achieve high overall resolution without requiring either divider to operate beyond its optimal frequency range, thus avoiding excessive power consumption while maintaining timing accuracy.
Solution Approach 2:
The patent introduces a temporal dimension by using different operating frequencies at different time stages in the frequency division process. The first divider operates at a base frequency for stable, low-power coarse division, while the second divider operates at a higher frequency only when needed for fine resolution. This dimensional approach to frequency management resolves the contradiction between accuracy and power consumption.
2Measurement precision
If the resolution of the frequency divider is increased to improve output clock accuracy, then the minimum swing step decreases, but the device complexity increases
Solution Approach 1:
The patent divides the frequency division function into two separate dividers with distinct roles: the first divider handles the bulk frequency reduction at lower complexity, while the second divider provides the necessary fine-grained control for high resolution. This segmentation allows each divider to be optimized independently, reducing the overall device complexity compared to a single high-resolution divider.
Solution Approach 2:
The patent merges the output of the first frequency divider with a phase signal from the phase-locked loop to drive the second frequency divider. This combination allows the system to leverage the stable baseline frequency from the first divider while adding the precision control of the second divider, achieving high output clock accuracy without the complexity of a single monolithic high-resolution divider.
3Measurement precision
If a higher resolution Δ-Σ modulator is used to improve SSCG performance at lower spectrum amplitudes, then the timing accuracy improves, but the device complexity and power consumption increase
Solution Approach 1:
The patent segments the resolution enhancement function across two frequency dividers rather than concentrating it in a single high-resolution Δ-Σ modulator. The first divider provides coarse frequency steps, while the second divider provides fine frequency steps, collectively achieving the resolution improvement that would otherwise require a complex high-bit Δ-Σ modulator, thus reducing device complexity.
Solution Approach 2:
The patent changes the operational parameters of the two frequency dividers dynamically: the first divider operates with a larger frequency step size for efficiency, while the second divider operates with a smaller frequency step size for precision. This parameter differentiation allows the system to achieve high timing accuracy without requiring a single high-complexity modulator, as each divider is optimized for its specific resolution requirement.
Data Source
AI summary
A method and apparatus for generating a spread spectrum reference clock is presented. A method and apparatus is presented for receiving a spread spectrum parameter from a phase lock loop, wherein the spread spectrum parameter includes a multiple-level parameter comprising a plurality of phase signals; quantizing a spread spectrum profile associated with the spread spectrum parameter; mapping the quantized profile; generating control signals based on the mapping, wherein the control signals include an integer control signal and a phase control signal; dividing a phase signal of the plurality of phase signals with the integer control signal; synchronizing the divided phase signal using the phase control signal; and providing a reference clock for a spread spectrum clock generator based on the synchronizing.