Spread Spectrum Fault Detection Using Sub-Chip Time Segmentation
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Solution Overview
Problem
Existing spread spectrum systems are ineffective in detecting faults in short wires used in life-critical medical devices due to the constraint that the chip time of the spread spectrum signal must be greater than the round-trip time for signals to travel over the wire, limiting their ability to locate faults closer than one chip time.
Innovation Solution
A system that delays a pseudo-random PN code by a series of sub-chip time delays, sums the delayed samples with the original PN code, and transmits the summed sequence down the wire, allowing for the detection of faults by mixing and integrating the received signal with a delayed copy of the summed sequence to map fault indications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the chip time of the spread spectrum signal is reduced to detect faults in short wires, then the fault detection resolution is improved, but the constraint that chip time must be greater than round-trip time causes the system to become ineffective
Solution Approach 1:
The patent segments the chip time into multiple smaller time slots, each capable of detecting faults in shorter wire segments. By dividing the original chip time Tc into N smaller time slots of duration Tc/N, the system can resolve faults at a finer granularity while maintaining the overall spreading gain necessary for reliable detection.
Solution Approach 2:
The patent introduces a new dimension of time slot indexing within each chip period. Instead of using a single time dimension for fault detection, the system creates a two-dimensional structure where each chip time contains multiple time slots, allowing simultaneous detection across different wire length scales and overcoming the fundamental time constraint.
2Device complexity
If conventional spread spectrum systems are used with short wires, then the system structure remains simple, but the ability to locate faults closer than one chip time is lost
Solution Approach 1:
The patent divides each chip period into multiple detectable time slots, creating N virtual measurement points within a single chip time window. This segmentation allows the system to achieve N times better fault location precision without adding proportional hardware complexity, as the segmentation is implemented through signal processing.
Solution Approach 2:
The patent changes the temporal parameter structure by introducing time slot indices within each chip period. This parameter transformation allows the system to map faults with precision much finer than the original chip time, effectively scaling the measurement resolution without requiring proportionally faster signaling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables high-resolution fault detection and sensitivity on short wires, allowing for early prediction of failure in medical devices such as defibrillators and artificial heart pumps, with the ability to detect faults within inches rather than feet, improving reliability and safety.
Implementation Method 1
a reflected signal is delayed by time. The reflected signal correlated to determine the characteristics and fault location of the wires
Implementation Method 2
The reflected signal correlated to determine the characteristics and fault location of the wires
Implementation Method 3
mixing the signal received from the wire with a delayed copy of the summed PN sequence so as to form a mixed signal
Implementation Method 4
integrating the mixed signal to map faults so as to detect indications of failures
Data Source
AI summary
There are disclosed systems and methods of determining a fault location on a wire. In an embodiment, a system includes a PN code having a chip-time. Software code is provided for delaying the PN code a series of delays to form delayed PN samples, a sum of the series of delays being less than one chip-time. Software code is provided for summing the delayed PN samples with the PN code to form a summed sequence. Software code is provided for transmitting the summed PN sequence to the wire. Software code is provided for receiving a signal from the wire related to the summed PN sequence. Software code is provided for mixing the signal received from the wire with a delayed copy of the summed PN sequence so as to form a mixed signal. Software code is provided for integrating the mixed signal to map faults. Other embodiments are also disclosed.