Spread Spectrum MII Clocking for Ethernet EMI Reduction
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Solution Overview
Problem
Existing Ethernet communication devices face challenges in reducing electromagnetic interference (EMI) at the digital processing portion, as traditional EMI reduction schemes primarily focus on the transmission medium and neglect the digital domain.
Innovation Solution
Implementing a spread spectrum clocking scheme at the Media Independent Interface (MII) of the Ethernet PHY, using a clock modulator to generate a spread spectrum MII clock, which synchronizes incoming data between the input clock domain and the spread-spectrum clock domain through an elasticity buffer, thereby reducing EMI at the digital interface between the Ethernet PHY and the MAC device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If traditional clocking schemes are used at the MII interface, then data transmission is simple and direct, but electromagnetic interference (EMI) power is high and exceeds FCC regulations
Solution Approach 1:
The patent applies spread spectrum clocking by deliberately modulating the clock frequency to vary continuously around the desired frequency, spreading the clock signal power over a broader frequency band. This parameter change in the clock signal characteristics reduces peak EMI power while maintaining data transmission functionality, directly resolving the contradiction between high EMI and transmission simplicity.
Solution Approach 2:
The invention introduces dynamic frequency modulation of the MII clock signal, where the clock frequency varies continuously rather than remaining fixed. This dynamic approach spreads the spectral energy distribution, reducing peak EMI emissions while maintaining adequate data transmission rates, thus resolving the contradiction between EMI reduction and transmission performance.
2Object-affected harmful factors
If spread spectrum clocking is applied at the MII interface, then EMI power is reduced by up to 10 dB, but the clock signal bandwidth increases
Solution Approach 1:
The patent deliberately changes the frequency parameter of the MII clock signal by applying spread spectrum modulation, causing the clock to vary continuously around the desired frequency. This parameter change spreads the spectral energy over a broader band, achieving EMI reduction of up to 10 dB while accepting increased bandwidth as a necessary trade-off for regulatory compliance.
3Reliability
If spread spectrum clocking is implemented without elasticity buffer, then device complexity is reduced, but data integrity cannot be ensured during clock domain translation
Solution Approach 1:
The patent introduces an elasticity buffer as an intermediary component between the spread spectrum clock domain and the input clock domain. This buffer absorbs the frequency variations and timing uncertainties introduced by spread spectrum clocking, ensuring reliable data transfer while maintaining data integrity. The intermediary buffer resolves the contradiction by providing the necessary decoupling between the two clock domains.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces EMI by spreading the MII clock, achieving a peak EMI power reduction of up to 10 dB, without requiring modifications to the MAC device and ensuring data integrity through appropriate clock spreading factors.
Implementation Method 1
Spread spectrum clocking refers to techniques by which a clock signal having a desired clock frequency is deliberately spread in the frequency domain, resulting in a signal with a wider bandwidth. Typically, the clock signal varies continuously around the desired frequency to spread out the bandwidth of the clock signal over a broader band of frequencies centered at the desired frequency.
Data Source
AI summary
A network device includes a physical layer transceiver configured to receive incoming data on a data link at an input clock rate and to store the incoming data in a buffer. The physical layer transceiver includes a Media Independent Interface (MII) controller configured to receive the incoming data stored in the buffer and to transmit the incoming data over a MII bus based on a MII clock where the MII clock is a spread spectrum clock. The network device further includes a Media Access Control (MAC) device configured to receiving incoming data from the physical layer transceiver over the MII bus where the incoming data is clocked by the spread spectrum MII clock.