Spread Spectrum PLL Loop Filter With Switched-Capacitor Resistance
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Solution Overview
Problem
Existing spread spectrum clock generators (SSCGs) in system on chip (SoC) devices face challenges due to the mismatch in fabrication processes of resistors and capacitors, leading to degraded performance in Electromagnetic Interference (EMI) suppression and increased jitter, primarily because on-die components do not track well, resulting in bulky capacitors and area consumption issues.
Innovation Solution
A process-independent SSCG is implemented using a discrete-time capacitance multiplier loop filter with switched capacitor resistors and a calibrated voltage-controlled oscillator (VCO) in combination with a scaled current reference, which maintains constant PLL control loop gain, improving performance by reducing area consumption and enhancing EMI suppression.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If on-die resistors and capacitors are used in the loop filter, then the PLL control loop can be stabilized with poles and zeroes, but the components do not track with process leading to degraded EMI suppression and increased jitter
Solution Approach 1:
The patent changes the parameters of the loop filter by using switched capacitor circuits to emulate resistors, allowing the resistance value to be defined by capacitance and switching frequency rather than physical resistor geometry. This enables better process tracking since capacitors and switches can be designed to track together through common-centroid layout techniques and matched fabrication processes.
Solution Approach 2:
The patent substitutes physical resistors with switched capacitor equivalents. Instead of using ohmic resistance from physical resistor materials, the patent uses the equivalent resistance created by charging and discharging capacitors through switches at specific frequencies. This substitution allows the resistance to be defined by capacitive values and timing, which can track better with process variations.
2Object-affected harmful factors
If low PLL bandwidth is used to filter quantization noise in digital delta sigma modulators, then EMI is reduced, but bulky on-chip capacitors are required leading to prohibitive area consumption
Solution Approach 1:
The patent changes the approach to achieving low PLL bandwidth by using switched capacitor resistors with precise timing control. Instead of relying on large physical capacitors to set the time constant, the patent uses the product of switched capacitor resistance and smaller capacitors, where the resistance is controlled by switching frequency and duty cycle. This allows the same time constant to be achieved with much smaller physical capacitor area.
Solution Approach 2:
The patent employs periodic switching action to create the equivalent resistance in the loop filter. By switching capacitors at specific frequencies and duty cycles, the patent generates an effective resistance value that can be precisely controlled through timing parameters rather than physical dimensions. This periodic action enables low PLL bandwidth with reduced capacitor area.
3Object-generated harmful factors
If fractional-N PLL with digital delta sigma modulator is used for spread spectrum clock generation, then EMI suppression is achieved, but quantization noise requires low loop bandwidth mandating bulky capacitors
Solution Approach 1:
The patent changes how the loop filter parameters are defined by using switched capacitor circuits where resistance is a function of switching frequency and capacitance ratio rather than physical resistor dimensions. This allows the loop bandwidth to be set by timing parameters that can be programmed or adjusted without changing physical capacitor sizes, thereby reducing the area required for achieving the necessary low bandwidth to filter DDSM quantization noise.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution achieves improved SSCG performance by maintaining constant PLL control loop gain, reducing area consumption, and enhancing EMI suppression, while ensuring process independence and decreased jitter.
Implementation Method 1
the loop filter is replaced with a discrete-time capacitance multiplier loop filter
Implementation Method 2
An embodiment of a process independent spread spectrum clock generator (SSCG) uses a combination of switched capacitor resistors for a capacitance multiplier loop filter
Implementation Method 3
a calibrated voltage controlled oscillator (VCO) in combination with a scaled current reference, which maintains constant PLL control loop gain
Implementation Method 4
spread spectrum clock generators (SSCGs) are usually implemented as fractional-N, phase locked loops (PLLs)
Data Source
AI summary
In one embodiment, a spread spectrum clock generator, comprising a digital delta sigma modulator coupled to a fractional N, phase locked loop (PLL), the PLL comprising a discrete-time capacitance multiplier loop filter, the discrete-time capacitance multiplier loop filter comprising: an amplifier comprising a non-inverting input and an inverting input; a first switched capacitor resistor and a capacitor coupled to the non-inverting input, the capacitor coupled between the first switched capacitor resistor and the non-inverting input; and a second switched capacitor resistor coupled to the inverting input.