Spread-Spectrum PLL Clocking With Noise Shaping for Flat EMI
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Solution Overview
Problem
Existing spread spectrum clock generation methods are ineffective in achieving spectral flatness and are costly in terms of silicon area for integrated circuit implementation, struggling to comply with stringent EMI/EMC standards while operating at high clock frequencies.
Innovation Solution
A spread spectrum clock generation system utilizing a Digital Frequency Profile Generator and a multilevel error feedback noise shaping structure, which provides spectral flatness with minimal silicon area usage by sharing hardware for both center-spread and down-spread modes, and translating modulation depth-dependent offset compensation to a static correction, thus reducing hardware requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If spread spectrum techniques are used to reduce EMI emissions, then EMI compliance is improved, but silicon area increases due to separate profile generators for different modes
Solution Approach 1:
The patent implements a universal Digital Frequency Profile Generator that can operate in both center-spread mode and down-spread mode using the same hardware circuitry. The generator receives a mode selection signal and configures itself accordingly, eliminating the need for separate profile generators for each mode. This multi-functional approach reduces silicon area while maintaining the ability to provide spectral flatness and reduce EMI emissions in both operating modes.
2Measurement precision
If look-ahead circuit is implemented for dynamic offset compensation, then frequency accuracy is improved, but device complexity increases due to arithmetic logic units
Solution Approach 1:
The patent pre-calculates and stores offset compensation values in a lookup table during the design phase, rather than performing dynamic calculations during operation. The Digital Frequency Profile Generator retrieves pre-computed offset values based on the configured modulation depth, avoiding the need for complex arithmetic logic units and look-ahead circuits. This approach maintains frequency accuracy while significantly reducing device complexity and silicon area.
3Manufacturing precision
If high resolution profile generator is used for precise frequency modulation, then spectral flatness is improved, but silicon area increases due to wide bit width requirements
Solution Approach 1:
The patent introduces a Sigma-Delta modulator as an intermediary between the low-resolution profile generator output and the PLL frequency control input. The Sigma-Delta modulator converts the coarse quantized values into a high-resolution frequency modulation signal through noise shaping and oversampling. This intermediary approach enables spectral flatness equivalent to high-resolution direct generation while using only low-resolution hardware, thereby reducing silicon area.
Data Source
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AI summary
The present invention provides a spread spectrum clock generation system, comprising a digitally controlled Phase Locked Loop (PLL), and a Digital Frequency Profile Generator to create a near optimal frequency modulation profile for the purpose of achieving spectral flatness in the output frequency modulated clock. The circuit is combined with a multilevel error feedback noise shaping structure that provides the required Noise Transfer Function for the quantization noise but maintains a unity gain all pass signal transfer function. This arrangement offers minimal degradation of the in-band Signal-to-Noise-Ratio (SNR) at the cost of higher out-of-band noise.