Spread Switching Times for Simultaneous Switching Noise Reduction
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Solution Overview
Problem
Current optimization techniques for Simultaneous Switching Noise (SSN) in Field Programmable Gate Array (FPGA) designs are manual, time-consuming, and lack flexibility, as they rely on iterative signoff analysis tools that do not provide enough information for Computer Aided Design (CAD) tools to perform optimizations effectively, leading to increased design time and suboptimal results.
Innovation Solution
The method involves using a CAD tool to receive value assignments for IC parameters, determining minimum and maximum path delays for I/O pins, spreading out actual switching times within these delays to reduce SSN, and routing paths to meet these conditions, allowing for automatic optimization of SSN without user intervention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If manual iterative optimization techniques are used for SSN, then design flexibility and control are maintained, but design time increases prohibitively and optimization quality decreases
Solution Approach 1:
The CAD tool automatically performs SSN optimization by internally determining minimum and maximum path delays and spreading switching times, eliminating the need for manual iterative operations while maintaining optimization quality
Solution Approach 2:
The system pre-calculates minimum and maximum path delays for all I/O pins before finalizing the design, allowing the CAD tool to automatically determine optimal switching times without requiring iterative manual adjustments during the design process
2Measurement precision
If signoff SSN analysis tools are used for optimization, then accurate SSN measurement is achieved, but the tools lack flexibility and require prohibitively long iteration times
Solution Approach 1:
The CAD tool is enhanced to perform multiple functions: it not only designs the IC but also automatically performs SSN analysis and optimization by determining path delays and spreading switching times, replacing the need for separate signoff analysis tools
Solution Approach 2:
The system uses internal feedback loops where the CAD tool continuously monitors path delays and adjusts switching times accordingly, allowing for automatic optimization without requiring external signoff analysis tools and their lengthy iteration processes
3Extent of automation
If CAD tools are given more information for automatic optimization, then design time reduces and automation increases, but the complexity of the optimization problem increases
Solution Approach 1:
The optimization problem is segmented into manageable sub-tasks: determining minimum path delays, determining maximum path delays, and spreading switching times based on these delays. This segmentation allows the CAD tool to handle the complexity systematically through automated algorithms
Data Source
AI summary
Methods and apparatus for reducing simultaneous switching noise (SSN) in an integrated circuit (IC) designed with a computer aided design (CAD) tool are presented. In one method, value assignments for parameters of the IC are received by the CAD tool. The value assignments are entered as a range of value assignments or as a list of possible value assignments. Further, the method includes an operation for determining the minimum and the maximum path delays for each Input/Output (I/O) pin in an I/O block such that the received value assignments are satisfied. The actual switching times of the I/O pins are spread out in time to decrease SSN in the I/O pins. The switching times are spread out so that the switching times fall between the minimum and the maximum path delay for the corresponding I/O pin. Additionally, other method operations are included for routing paths to the I/O pins to meet the actual switching times and for creating a design for the IC that meets the actual switching times.