Spurious Signal Detection Logic for Secure Data Processing

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Solution Overview

Problem

Existing data processing systems lack effective mechanisms to detect unexpected or spurious signals, which can indicate attacks or errors, particularly in secure systems like smart cards, where mechanical and logical protection mechanisms are insufficient.

Innovation Solution

A circuit with spurious signal detection logic that determines safe and transition time windows for digital signal values, outputting a detection signal if transitions occur outside these windows, enhancing security and robustness by identifying potential attacks or errors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If mechanical protection mechanisms are used to detect attacks, then security protection is provided, but the system cannot detect spurious signals at the circuit level

Engineering Contradiction:
Improvesecurity protectionVSAvoidspurious signal detection capability
Core Design Contradiction:
ReliabilityVSDifficulty of detecting and measuring

Solution Approach 1:

The patent replaces mechanical protection mechanisms with circuit-level detection logic that monitors signal transitions timing. The spurious signal detection logic uses timing windows to detect unexpected signal transitions that mechanical mechanisms cannot identify, thereby substituting mechanical detection with electronic/timing-based detection to achieve both security and spurious signal detection.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Difficulty of detecting and measuring

If circuit level detection is added to detect spurious signals, then detection capability is improved, but device complexity increases

Engineering Contradiction:
Improvespurious signal detection capabilityVSAvoidcircuit structure
Core Design Contradiction:
Difficulty of detecting and measuringVSDevice complexity

Solution Approach 1:

The patent segments the detection function into distinct timing windows (safe time window and transition time window) that are generated separately and then used by the spurious signal detection logic. This segmentation allows the complex detection task to be broken down into manageable timing intervals, reducing overall circuit complexity while maintaining detection capability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent generates timing windows in advance before spurious signal detection is needed. The safe time window and transition time window are pre-established based on expected signal behavior, allowing the detection logic to simply compare actual transitions against these pre-defined windows rather than performing complex real-time analysis, thereby reducing circuit complexity.

Inventive Principle:
Principle #10Preliminary action

3Measurement precision

If timing windows are defined for each clock cycle, then detection precision is improved, but processing time increases

Engineering Contradiction:
Improvetransition detection precisionVSAvoidprocessing time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent uses periodic timing windows that repeat each clock cycle with fixed durations for safe time window and transition time window. This periodic structure allows the detection logic to operate in a predictable, rhythmical manner rather than performing complex variable calculations each cycle, thereby maintaining high detection precision while minimizing processing time through regular, pre-determined timing intervals.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS7574314B2Spurious signal detection
Publication Date: 2009.08.11 ARM LTD
  • US7574314B2 patent drawing
  • US7574314B2 patent drawing
  • US7574314B2 patent drawing

AI summary

A circuit for a data processing apparatus and a method for detecting spurious signals is disclosed, the circuit comprising a data input operable to receive digital signal values, spurious signal detection logic operable to monitor a digital signal value within the circuit, and to determine at least one of: a safe time window during which it is expected that the digital signal values input into the circuit may cause data transitions in the monitored digital signal value and a transition time window in which it is expected a data transition will occur; and in response to detecting either a data transition in the monitored digital signal value outside of the at least one safe time window or no data transition in the transition window, the spurious signal detection logic is operable to output a detection signal.