SADP and SAQP Hybrid Patterning for SRAM Logic Cell Height Reduction
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Solution Overview
Problem
As semiconductor devices shrink, the height of SRAM cells remains constant due to self-aligned quadruple patterning (SAQP), limiting packing density due to fixed space between fins and cell height.
Innovation Solution
A method involving multiple spacer layers and etching processes to form vertical spacers over logic and SRAM areas, combining POR SAQP and SADP techniques to reduce cell height and increase packing density, allowing for varying fin spaces without dummy structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If self-aligned quadruple patterning (SAQP) is used to achieve small fin spacing, then fin spacing can be reduced to 48-82 nm, but cell height cannot shrink below approximately 270 nm
Solution Approach 1:
The patent divides the patterning process into two separate sections: logic area using SAQP for 48-82 nm spacing and SRAM area using SADP for larger spacing. This segmentation allows each area to use the most appropriate technique for its requirements, resolving the contradiction between achieving small fin spacing and maintaining manufacturable cell height.
Solution Approach 2:
Different patterning techniques are applied to different areas of the semiconductor device based on local requirements. The logic area uses SAQP for maximum density while the SRAM area uses SADP for easier manufacturing, allowing each region to have optimized characteristics for its specific function.
2Productivity
If SAQP is used to reduce fin spacing, then packing density improves, but cell height remains fixed at approximately 270 nm
Solution Approach 1:
The device is segmented into logic and SRAM areas with different patterning approaches. The logic area achieves high packing density through SAQP while the SRAM area uses SADP with larger, more manufacturable cell height, allowing the overall device to achieve high productivity without uniform cell height constraints.
Solution Approach 2:
The patent changes the critical dimensions and process parameters between the two patterning techniques. SAQP uses smaller mandrel dimensions and tighter process control for logic area, while SADP uses larger dimensions and relaxed parameters for SRAM area, enabling optimized packing density in logic while maintaining manufacturability in SRAM.
3Ease of manufacture
If uniform patterning technique is used across the entire device, then process simplicity is maintained, but flexibility to optimize different areas is lost
Solution Approach 1:
The manufacturing process is segmented into two distinct workflows: one for logic area and one for SRAM area. Each workflow is optimized for its specific requirements, with logic using SAQP for maximum density and SRAM using SADP for ease of manufacture. The segmentation allows both process simplicity and area-specific optimization to coexist.
Solution Approach 2:
Different process parameters, mandrel dimensions, and patterning techniques are applied locally to different areas based on their specific requirements. This allows the logic area to be optimized for density while the SRAM area is optimized for manufacturability, achieving both local quality and overall device performance.
Data Source
AI summary
Devices and methods of fabricating integrated circuit devices with reduced cell height are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a substrate including a logic area and an SRAM area, a fin material layer, and a hardmask layer; depositing a mandrel over the logic area; depositing a sacrificial spacer layer; etching the sacrificial spacer layer to define a sacrificial set of vertical spacers; etching the hardmask layer; leaving a set of vertical hardmask spacers; depositing a first spacer layer; etching the first spacer layer to define a first set of vertical spacers over the logic area; depositing an SOH layer; etching an opening in the SOH layer over the SRAM area; depositing a second spacer layer; and etching the second spacer layer to define a second set of spacers over the SRAM area.