Square Delay Line Circuit Layout for Uniform Timing
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Solution Overview
Problem
Conventional delay line circuits for system-on-chip (SoC) face challenges in achieving uniform delay steps, flexibility in layout, and stability across varying temperatures and voltages, leading to increased design complexity and cost.
Innovation Solution
A delay line circuit design featuring a fine delay unit and multiple coarse delay units with a square circuit layout, utilizing PMOS and NMOS transistors with equal gate feature widths, and dummy transistors to adjust delay steps, allowing for flexible placement and reduced parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional delay line circuit uses straight-line arrangement of fine delay unit and coarse delay units, then uniform delay steps can be achieved, but the circuit layout becomes complicated and space is wasted
Solution Approach 1:
The patent transforms the conventional straight-line arrangement into a two-dimensional square grid layout. The fine delay unit and coarse delay units are arranged in rows and columns, utilizing both horizontal and vertical dimensions for signal routing. This dimensional transformation maintains uniform delay steps through symmetric routing paths while significantly improving space utilization and reducing overall circuit area.
2Manufacturing precision
If different transistor sizes are used in fine delay unit to ensure accurate uniformity of delay steps, then delay uniformity is improved, but parasitic capacitance increases
Solution Approach 1:
The patent employs transistors with uniform gate feature widths throughout the delay line circuit, including in the fine delay unit. This homogeneity approach eliminates the need for varying transistor sizes to achieve delay uniformity. The symmetric square layout and equal-width transistor design work together to provide consistent delay steps without introducing additional parasitic capacitance from size-matched transistors.
3Reliability
If conventional delay line circuit design is used, then delay function is achieved, but design period is long and cost is high due to increased complexity
Solution Approach 1:
The patent creates a universal delay line circuit module with square symmetry that can be configured for different delay requirements through simple control signal selection. The standardized design with uniform transistors and symmetric layout serves multiple functions: fine delay adjustment, coarse delay adjustment, and phase control, all within a single integrated module. This universality reduces design complexity by eliminating the need for multiple specialized circuit designs.
Data Source
AI summary
A delay line circuit is provided and includes a fine delay unit and coarse delay units. Each fine delay circuit includes a first PMOS transistor; a first NMOS transistor; second PMOS transistors whose widths of gate features of the second PMOS transistor are equal; at least one third PMOS transistor, coupled between the power voltage and the source of the first PMOS transistor, whose width of gate features is smaller than the widths of the gate features of the second PMOS transistors, second NMOS transistors whose widths of gate features of the second NMOS transistors are equal; and at least one third NMOS transistor, coupled between the ground voltage and the source of the first NMOS transistor, whose width of gate features is smaller than the widths of the gate features of the second NMOS transistors.