Square I/O Cell Layout for Flexible Chip Placement
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Solution Overview
Problem
Conventional I/O pad cells are restricted to a single common poly direction, limiting their orientation and placement on a chip, which affects performance and restricts their use on adjacent sides, especially in deep sub-micron technologies below 28 nm.
Innovation Solution
Designing I/O cells with a substantially square shape, where the width and height dimensions are approximately equal, allowing for flexible orientation and reuse on all sides of the chip, and optimizing power and ground pin dimensions to facilitate shared bus structures and reduced RDL routing congestion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If I/O cells are designed with rectangular shape and single poly direction, then manufacturing is simplified, but placement flexibility and performance are limited
Solution Approach 1:
The patent applies universality by designing a single I/O cell layout that can be reused on all four sides of the chip with different orientations. The cell incorporates both vertical and horizontal power/ground buses that can serve as either top or bottom buses depending on orientation, allowing the same cell design to function universally across all chip peripheries without requiring side-specific variations.
Solution Approach 2:
The patent employs asymmetry by providing different power and ground bus configurations within the same cell layout - specifically, the cell has asymmetric power bus and ground bus arrangements that can be oriented differently depending on which side of the chip the cell is placed on, enabling flexible placement while maintaining functional correctness.
2Productivity
If I/O cells use traditional rectangular orientation, then more cells fit in the pad frame, but layout-dependent effects increase and performance decreases
Solution Approach 1:
The patent applies parameter changes by modifying the power and ground bus dimensions and configurations based on the cell orientation and location. The power bus and ground bus widths, spacings, and routing patterns are adjusted as parameters to optimize performance while maintaining adequate cell density in the pad frame.
3Manufacturing precision
If I/O cells are restricted to single poly direction, then manufacturing precision is maintained, but adaptability to different chip sides is reduced
Solution Approach 1:
The patent applies dimensionality change by introducing orientation as an additional dimension of flexibility. Instead of being constrained to a single poly direction, the cell design allows rotation to different orientations (0°, 90°, 180°, 270°) while maintaining manufacturing precision through consistent fabrication processes that can handle multiple orientations of the same base layout.
4Ease of manufacture
If power and ground pins use traditional dimensions, then manufacturing is easier, but RDL routing congestion increases
Solution Approach 1:
The patent applies parameter changes by optimizing power and ground pin dimensions, spacings, and routing configurations to reduce RDL routing congestion. The power bus and ground bus parameters are adjusted to provide adequate spacing for RDL routing while maintaining manufacturability through standard fabrication capabilities.
Data Source
AI summary
An I/O ring formed by a single type of I/O cell. The I/O cell has a substantially square shape in which the height and width dimensions are substantially equal. Each I/O cell has an X-axis and a Y-axis, where the two or more I/O cells are mounted adjacent on an axis by flipping every alternate I/O cell about another axis to share a vertical bus between the two I/O cells. Each I/O cell has a power pin portion and a ground pin portion to be dimensioned to be approximately one-half a designated power pin region and ground pin portion, respectively.