Square Pole Semiconductor Channel With Uniform Compressive Stress
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Solution Overview
Problem
Conventional semiconductor devices with fin-shaped channel portions face challenges in controlling carrier mobility due to fluctuations in compressive stress caused by variations in the thickness of the silicon germanium layer, leading to reduced carrier mobility and increased leakage current.
Innovation Solution
A semiconductor device with a square pole-shaped channel portion surrounded by gate electrodes on both sides, using a second semiconductor layer with a different lattice constant to form source and drain regions directly on the substrate, which are epitaxially grown to ensure uniform compressive stress across the channel portion, thereby enhancing carrier mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a silicon germanium layer is epitaxially grown on the remaining silicon layer to generate compressive stress, then carrier mobility is improved, but the thickness of the remaining silicon layer disperses causing the total amount of silicon germanium layer to disperse and the compressive stress to fluctuate
Solution Approach 1:
An etching stopper layer is formed on the substrate before the silicon layer is deposited and patterned. This stopper layer is positioned at a predetermined depth and serves as a reference plane for subsequent etching operations, ensuring that the remaining silicon layer has uniform thickness across the wafer. The stopper layer is formed in advance to establish a consistent baseline for the fin structure fabrication process.
Solution Approach 2:
The patent replaces thickness control based on etching depth variability with a reference-plane-based control system. Instead of relying on precise etching depth measurement, the etching stopper layer provides a physical reference plane that ensures uniform exposure of the remaining silicon layer, thereby enabling uniform epitaxial growth of the silicon germanium layer and consistent compressive stress application.
2Ease of manufacture
If the remaining silicon layer is made thin to allow complete epitaxial growth, then the source and drain regions can be fully formed, but the lower portion of the channel portion contacts no silicon germanium layer reducing strain and carrier mobility
Solution Approach 1:
The etching stopper layer acts as an intermediary reference plane that enables precise control of the remaining silicon layer thickness. By providing a predetermined depth reference, it allows the remaining silicon layer to be maintained at an optimal thickness that enables complete epitaxial growth of the silicon germanium layer while ensuring the lower portion of the channel portion remains in contact with the strained silicon germanium layer, thereby maintaining high carrier mobility throughout the entire channel.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves consistent and increased carrier mobility by uniformly applying compressive stress across the channel portion, reducing leakage current and improving device performance.
Implementation Method 1
A compressive stress is generated in a channel portion by the silicon germanium layer to give the channel portion a strain, thereby increasing a mobility of carriers
Implementation Method 2
a silicon germanium layer is epitaxially grown on the part of the silicon layer thus left
Data Source
AI summary
A semiconductor device according to an embodiment of the present invention includes: a square pole-shaped channel portion made from a first semiconductor layer formed on a substrate, and surrounded with four side faces; a gate electrode formed on a first side face of the channel portion, and a second side face of the channel portion opposite to the first side face through respective gate insulating films; a source region having a conductivity type different from that of the channel portion and being formed on a third side face of the channel portion, the source region including a second semiconductor layer having a lattice constant different from that of the first semiconductor layer and being formed directly on the substrate; and a drain region having a conductivity type different from that of the channel portion and being formed on a fourth side face of the channel portion opposite to the third side face, the drain region including the second semiconductor layer being formed directly on the substrate.