Square Root Circuitry Radix Segmentation
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Solution Overview
Problem
Existing digit recurrence algorithms for square root operations face challenges in balancing performance, circuit area, and power consumption, particularly when implementing higher radix operations, as they require complex circuitry and struggle to efficiently split higher-radix iterations into smaller-radix sub-iterations within a single processing cycle.
Innovation Solution
The approach involves performing a given radix-r iteration of a square root operation by splitting it into multiple radix-n sub-iterations within the same processing cycle, using digit selection, remainder update, and remainder estimate circuitry to generate and update values in parallel, thereby reducing timing delays and circuit complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a higher radix-r implementation is used to produce more result bits per iteration, then performance is improved, but circuit complexity increases
Solution Approach 1:
The patent divides a single complex radix-r iteration into multiple simpler radix-n sub-iterations. Each sub-iteration processes a portion of the result bits, breaking down the complex circuit into manageable segments that can be executed sequentially within the same processing cycle. This segmentation reduces the complexity of individual circuit blocks while maintaining the overall productivity gain.
2Productivity
If more radix-n sub-iterations are performed in parallel within a single processing cycle, then performance is improved, but timing constraints become more difficult to meet
Solution Approach 1:
The patent performs preliminary actions by pre-calculating and preparing data for multiple sub-iterations before they are executed. Remainder estimates and other intermediate values are computed in advance, allowing the sub-iterations to proceed with minimal delay. This preliminary preparation reduces the critical path timing constraints while enabling parallel execution of multiple sub-iterations.
3Productivity
If complex circuitry is used to perform higher radix operations directly, then performance is improved, but power consumption increases
Solution Approach 1:
By segmenting the higher radix operation into multiple lower radix sub-iterations, the patent reduces the complexity and power consumption of individual circuit blocks. Each sub-iteration uses simpler logic that consumes less power, while the cumulative effect of multiple sub-iterations achieves the same productivity as a single complex operation.
Data Source
AI summary
Square root processing circuitry performs a given radix-r iteration of a radix-r square root operation, by performing multiple radix-n sub-iterations in a same processing cycle, where n<r. The square root processing circuitry comprises, for a given radix-n sub-iteration: digit selection circuitry to select, based on a previous remainder estimate, a next radix-n result digit for a square root result; remainder update circuitry to adjust a previous remainder value to generate an updated remainder value; and remainder estimate circuitry to generate an updated remainder estimate indicative of an estimate of a portion of the updated remainder value. In a final radix-n sub-iteration of the given radix-r iteration, the remainder estimate circuitry generates the updated remainder estimate in parallel with the remainder update circuitry generating the updated remainder value.