Square Root Unit Digit Splitting for Clock Frequency
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Solution Overview
Problem
The first iteration of square root calculations in microprocessors requires more cycles and larger multiplications than subsequent iterations, leading to increased delay and limiting clock frequency, and existing combined division and square root units do not efficiently utilize hardware for simultaneous operations.
Innovation Solution
The solution involves splitting the first digit of the square root into two parts for reduced multiplications, using a combined division/square root unit with shared hardware for simultaneous execution, and an improved multiply-and-accumulate unit for packed-single and double-precision operations, allowing for faster clock cycles and reduced chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the first iteration of square root calculations is performed with full precision multiplication, then calculation accuracy is maintained, but the delay in clock cycles increases and clock frequency is limited
Solution Approach 1:
The first digit of the square root is split into two parts, allowing the multiplication operations to be performed on smaller segments. This segmentation reduces the complexity and delay of the multiplication operations while maintaining the overall calculation accuracy through proper recombination of the segmented results.
2Area of stationary object
If a combined division and square root unit is implemented, then chip area is reduced, but hardware complexity increases
Solution Approach 1:
The same hardware unit is designed to perform both division and square root operations by utilizing the iterative nature of both algorithms. The unit can be configured to execute different operational modes, sharing common computational resources such as the multiply-and-accumulate unit, registers, and control logic between the two functions, thereby reducing overall chip area while managing hardware complexity through unified design.
3Device complexity
If the first digit of square root is not split, then the multiplication operations are simpler, but the delay in clock cycles increases
Solution Approach 1:
The first digit is divided into two parts so that multiplication operations can be performed on smaller values, reducing the critical path delay. The segmented multiplications are executed in parallel or in a pipelined manner, decreasing the overall time required for the first iteration while keeping the multiplication logic relatively simple.
4Productivity
If more hardware is allocated for simultaneous division and square root operations, then operational speed increases, but chip area increases
Solution Approach 1:
A single hardware unit is designed to handle both division and square root operations through configuration control. The unit shares critical resources such as the multiply-and-accumulate unit, data paths, and computational logic between the two operations. By time-multiplexing or mode-switching between division and square root functions, the design achieves simultaneous operational capability without duplicating hardware, thus maintaining high productivity while minimizing chip area.
Data Source
AI summary
Square root operations in a computer processor are disclosed. A first iteration for calculating partial results of a square root operation is performed in a larger number of cycles than remaining iterations. The first iteration requires calculation of a first digit that is larger than the subsequent digits. The first iteration thus requires multiplication of values that are larger than corresponding values for the subsequent other digits. By splitting the first digit into two parts, the required multiplications can be performed in less time than if the first digit were not split. Performing these multiplications in less time reduces the total delay for clock cycles associated with the first digit calculations, which increases the possible clock frequency allowed. A multiply-and-accumulate unit that performs either packed-single operations or double-precision operations may be used, along with a combined division/square root unit for simultaneous execution of division and square root operations.