Squaring Circuit Segmentation for Power Detection Accuracy
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Solution Overview
Problem
Conventional wireless communication systems face challenges with power detection due to sensitivity to DC offsets and noise gain issues in squaring circuits, limiting the dynamic range and requiring complex temperature compensation, especially in wideband applications.
Innovation Solution
A squaring circuit utilizing current mode triplet MOS devices with differential input and output ports, configured to provide a constant gain response across frequencies, and a calibration method to compensate for temperature variations and DC offsets, allowing for accurate power detection with reduced complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional squaring circuits are used for power detection, then power detection capability is provided, but sensitivity to DC offsets and noise gain issues limit the dynamic range
Solution Approach 1:
The squaring circuit is segmented into multiple parallel paths: a main path with a first squarer for the majority of the signal and auxiliary paths with second squarers for correction. This segmentation allows the circuit to handle DC offsets and noise gain issues separately, improving dynamic range without requiring complete redesign of the entire squaring function.
Solution Approach 2:
An intermediary correction circuit is introduced that processes the output of the main squarer and adds correction terms to compensate for DC offset and noise gain errors. This intermediary stage acts as a mediator between the main squaring function and the final power detection output, improving accuracy without significantly increasing overall complexity.
2Stability of the object's composition
If temperature compensation is implemented in squaring circuits, then temperature stability is improved, but circuit complexity increases
Solution Approach 1:
The circuit employs self-compensation mechanisms where the correction paths automatically adjust for temperature variations through their inherent design. The auxiliary squarers and correction circuits are configured to naturally counteract temperature-induced drifts without requiring external temperature sensors or complex compensation networks, achieving temperature stability while maintaining relatively simple circuitry.
3Adaptability or versatility
If wideband operation is supported, then frequency range is extended, but noise sensitivity and temperature dependence increase
Solution Approach 1:
The wideband squaring circuit is divided into multiple frequency-dependent paths with different squarers optimized for different portions of the frequency range. Each path handles specific frequency bands with appropriate noise characteristics, allowing the overall circuit to maintain low noise sensitivity across the entire wideband operation while extending the supported frequency range.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves a highly accurate square-law transfer function with reduced noise sensitivity and minimal temperature dependence, enabling efficient power detection across a wide frequency range with improved dynamic range and simplified circuitry.
Implementation Method 1
the square-law relationship of the drain-current, ID, to gate-source voltage, VGS, of a MOS transistor operating in the saturation region
Data Source
AI summary
A squaring circuit has current mode triplet metal oxide semiconductor (MOS) devices, including a first MOS device, a second MOS device and a third MOS device each having a source operably coupled to a first current source; and a fourth MOS device, a fifth MOS device and a sixth MOS device each having a source operably coupled to a second current source. The drain of first and fourth MOS device is operably coupled to a first supply, the drain of second and fifth MOS device is operably coupled to a first differential output port and the drain of third and sixth MOS device is operably coupled to a second differential output port. The gate of first, second and sixth MOS device is connected to a first differential input port, and the gate of third, fourth and fifth MOS device is connected to a second differential input port.