Synchronous Rectification Control for Power Saving
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Power conversion apparatuses with synchronous rectification (SR) transistors face reduced conversion efficiency due to power consumption when the load is in a light load status, primarily because of the SR controller charging or discharging the parasitic capacitor and the SR transistor's own power consumption.
Innovation Solution
A power conversion apparatus with an SR control circuit that determines the load status by analyzing the time interval or cycle time of the SR transistor or parasitic diode being turned on, allowing it to enter a power-saving mode and turn off the SR transistor when in light load conditions, thereby reducing unnecessary power consumption and improving efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If an SR transistor is used to replace the rectification diode to reduce power consumption, then the power consumption is reduced, but the conversion efficiency is reduced when the load is in a light load status due to the SR controller charging or discharging the parasitic capacitor and the SR transistor's own power consumption
Solution Approach 1:
The patent applies dynamics by making the SR transistor's operating state changeable between on-state and off-state based on load conditions. The control circuit dynamically adjusts the SR transistor's state: keeping it on during moderate to heavy loads to achieve synchronous rectification with low Rds-on, and turning it off during light loads to eliminate parasitic capacitor charging/discharging losses. This dynamic adaptation resolves the contradiction between low power consumption and high conversion efficiency across different load conditions.
Solution Approach 2:
The patent changes the operating parameters of the SR transistor based on load status. By detecting load conditions and adjusting the gate control signal, the SR transistor switches between conducting and non-conducting states. This parameter change allows the system to optimize between two operating modes: synchronous rectification mode for high efficiency at moderate/heavy loads, and power-saving mode for minimal losses at light loads, thereby resolving the efficiency-power consumption contradiction.
2Use of energy by moving object
If the SR transistor is kept on to maintain low Rds-on for synchronous rectification, then power consumption is reduced, but unnecessary power consumption occurs during light load status
Solution Approach 1:
The system dynamically adjusts the SR transistor's on/off state based on real-time load detection. The control circuit monitors load conditions and transitions the SR transistor from a continuously-on state to a conditionally-on state. During light loads, the transistor is turned off to eliminate unnecessary power consumption, while during moderate to heavy loads, it remains on to provide low Rds-on for efficient synchronous rectification. This dynamic control resolves the contradiction between maintaining low resistance and avoiding unnecessary power consumption.
Solution Approach 2:
The control circuit automatically detects load status and autonomously controls the SR transistor's operating state without external intervention. The system self-adjusts by monitoring its own operating conditions and making appropriate control decisions, turning off the SR transistor during light loads to eliminate wasted power while maintaining efficient operation during heavier loads, thereby resolving the unnecessary power consumption issue.
3Ease of operation
If the SR controller charges or discharges the parasitic capacitor during switching, then the SR transistor can be controlled, but power consumption occurs that reduces conversion efficiency during light load status
Solution Approach 1:
The patent extracts the parasitic capacitor charging/discharging operation from the continuous control process by selectively disabling the SR transistor during light load conditions. Instead of continuously managing the parasitic capacitor, the system removes the SR transistor from the circuit during light loads, thereby eliminating the associated power losses. This extraction approach maintains full control capability during moderate to heavy loads while eliminating unnecessary energy consumption during light loads, resolving the contradiction between control capability and energy efficiency.
Data Source
AI summary
A power conversion apparatus is provided. The power conversion apparatus includes a transformer, a synchronous rectification (SR) transistor and an SR control circuit. A first terminal of a primary side of the transformer receives an input voltage. A first terminal of a secondary side of the transformer provides an output voltage to a load. A first drain/source terminal of the SR transistor is coupled to a second terminal of the secondary side of the transformer. A second drain/source terminal of the SR transistor is coupled to a first ground terminal. A gate terminal of the SR transistor receives a control signal. The SR control circuit receives a signal of the first drain/source terminal of the SR transistor to determine statuses of the load and generate the control signal. When the load is a light load, the SR control circuit enters a power-saving mode and turns off the SR transistor.