SR Flex Algorithm Plane for Latency-Sensitive L1 Services

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Solution Overview

Problem

Existing solutions for providing low latency paths in Segment Routing (SR) networks are inefficient, requiring large segment identifier (SID) label stacks and being configuration intensive, while also lacking dynamicity to adapt to changes in network latency.

Innovation Solution

The implementation of a Flex Algorithm Definition (FAD) for latency information, shared via a new sub-Type-Length-Value (TLV), dynamically builds a flex algo plane that provides a traffic-engineered view of the network, restricting SID stack scope and automatically adjusting with network events.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If colored links are used to compute low latency paths in SR network, then latency sensitivity is improved, but SID stack depth increases to unusable sizes

Engineering Contradiction:
ImprovelatencyVSAvoidSID stack depth
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent implements dynamic latency measurement and advertisement mechanisms where latency values are continuously updated based on actual network conditions. The system dynamically adjusts the flex-algo plane based on measured latency from lower layers, allowing the network to adapt to changing conditions without requiring static, overly complex SID stacks.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the approach from using colored links with fixed attributes to using flex-algo with dynamic latency parameters. By advertising latency values through IGP and using them to compute paths, the system achieves latency sensitivity without the complexity of colored link implementations.

Inventive Principle:
Principle #35Parameter changes

2Device complexity

If multiple SR policies are stitched together to avoid large SID stacks, then SID stack size is reduced, but configuration complexity increases significantly

Engineering Contradiction:
ImproveSID stack sizeVSAvoidconfiguration complexity
Core Design Contradiction:
Device complexityVSEase of manufacture

Solution Approach 1:

The patent creates a universal flex-algo plane that can be used across the entire SR network for latency-sensitive services. Instead of stitching together multiple specific SR policies, the system implements a single multi-functional flex-algo mechanism that handles latency computation uniformly throughout the network, reducing configuration complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system implements feedback loops where latency information is measured, advertised through IGP, used to compute paths, and then used to dynamically adjust the flex-algo plane. This automated feedback mechanism eliminates the need for manual configuration of multiple policies.

Inventive Principle:
Principle #23Feedback

3Loss of information

If packet level latency information is collected, then latency computation is enabled, but accuracy is insufficient for low latency services

Engineering Contradiction:
Improvelatency information availabilityVSAvoidlatency accuracy
Core Design Contradiction:
Loss of informationVSMeasurement precision

Solution Approach 1:

The patent uses lower layer networks as intermediaries to provide accurate latency measurements. Instead of relying on packet-level measurements at layer 3, the system retrieves latency information from lower layers (layer 1/2) which have more accurate timing capabilities, and uses this information in the layer 3 routing decisions.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS12316534B2Latency sensitive network plane via SR flex algorithm for layer 1 services
Publication Date: 2025.05.27 CIENA CORP
  • US12316534B2 patent drawing
  • US12316534B2 patent drawing
  • US12316534B2 patent drawing

AI summary

Systems and methods include maintaining a network plane in Segment Routing (SR) Flexible Algorithm having a Flexible Algorithm Definition (FAD) based on latency; receiving a request for a service over a SR network where the service is sensitive to a specific latency; and determining a label stack including one or more Segment Identifiers (SID) for the service, with the one or more SIDs based on the network plane in SR Flexible Algorithm. This can be used for Private Line Emulation (PLE) services and Circuit Emulation (CEM) services over SR, ensuring latency while not requiring large label stacks.