SR Latch Clock Gating Cell With Lower Power and Area
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Solution Overview
Problem
Integrated circuits face challenges in reducing power consumption and area while effectively gating clock signals to prevent malfunction and maintain high efficiency.
Innovation Solution
A clock gating cell design utilizing a set-reset (SR) latch structure with specific logic gates and transistors, including 2-input and 4-input logic gates, NAND gates, and an OR-AND-INVERTER (OAI) gate configuration, which reduces the number of transistors and input capacitance to minimize power consumption and delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a conventional clock gating cell is used to stop and resume clock signal supply, then clock gating function is achieved, but power consumption and area are high
Solution Approach 1:
The patent combines the clock gating function with an SR latch structure, merging the clock signal control path with the data path through shared transistors. The first and second NFETs are shared between the latch circuit and the clock gating logic, reducing total transistor count while maintaining reliable clock signal management through the latch's memory function.
Solution Approach 2:
The SR latch structure serves multiple functions: it stores the enable signal state, controls the clock signal passage, and provides feedback for stable operation. The cross-coupled NFETs and NOR gates create a universal control mechanism that handles both data latching and clock gating in a single circuit block.
2Loss of energy
If the number of transistors is reduced to lower power consumption, then power efficiency improves, but device complexity increases
Solution Approach 1:
The patent merges multiple functions into a compact structure where the SR latch and clock gating logic share transistors. The first NFET is shared between the latch pull-down network and the clock gating pull-down network, and the second NFET is shared between the latch and the enable control logic, reducing total transistor count while maintaining functionality.
Solution Approach 2:
The circuit is segmented into functional blocks (SR latch portion and clock gating portion) that are interconnected through shared transistors. This segmentation allows independent analysis of each function while the shared components create efficient overlap that reduces overall complexity.
3Area of stationary object
If a compact clock gating cell is designed to reduce area, then area efficiency improves, but power consumption increases
Solution Approach 1:
The patent achieves area reduction by merging the SR latch and clock gating functions into a single integrated circuit block. The shared transistors (first and second NFETs) are located at strategic points where they serve dual purposes, reducing the total silicon footprint while the efficient logic design minimizes dynamic power consumption through reduced switching activity.
Data Source
AI summary
In an integrated circuit including a clock gating cell based on a set-reset (SR) latch, the clock gating cell includes a first 2-input logic gate configured to receive a clock input and a first signal, and generate a second signal, a first inverter configured to receive the second signal, and generate a clock output, and a 4-input logic gate including a 4-input keeping logic gate configured to generate the SR latch by being cross-coupled to the first 2-input logic gate and keep a level of the first signal.