SR-Latch Duty Cycle Corrector for Stable 50% Output Clocks
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Solution Overview
Problem
Traditional duty cycle correctors face instability in output clocks due to manufacturing variations and increased power consumption when the input clock duty cycle is not 50%, leading to short currents between work and ground voltages.
Innovation Solution
A duty cycle corrector comprising an SR latch generating control signals and two switches, one between the work voltage and output node, and the other between the output node and ground, ensuring a stable output clock with reduced power consumption by preventing simultaneous closure of switches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional duty cycle corrector circuits are used, then the output clock duty cycle can be corrected to 50%, but the output clock becomes unstable due to manufacturing process variations
Solution Approach 1:
The patent changes the operating parameters of the circuit by using complementary clock signals (CLK and CLK_B) with opposite phases to control the switches. This parameter change ensures that the output clock maintains stable 50% duty cycle regardless of manufacturing variations, as the complementary control signals compensate for process variations in a manner similar to how differential signaling compensates for manufacturing tolerances in high-speed circuits.
Solution Approach 2:
The patent implements a feedback mechanism where the output clock is fed back to the SR latch, which generates control signals based on the phase relationship between the input clock and its complement. This feedback loop automatically adjusts the switching timing to maintain stable 50% duty cycle output, compensating for manufacturing variations through self-correcting behavior.
2Productivity
If traditional duty cycle corrector circuits are used, then the output clock can be generated, but power consumption increases due to short current when input clock duty cycle is not 50%
Solution Approach 1:
The patent applies preliminary anti-action by using complementary clock signals to preemptively prevent the short current condition. The SR latch generates control signals that ensure one switch is always open when the other is closed, based on the complementary phase relationship between CLK and CLK_B. This preliminary control action prevents the harmful short current from occurring in the first place, eliminating unnecessary power consumption while maintaining continuous output clock generation.
Data Source
AI summary
A duty cycle corrector includes an SR latch, a first switch and a second switch. The SR latch is configured to generate first and second control signals according to first and second clocks. The first switch is coupled between a work voltage and an output node, and selectively closes and opens according to the first control signal. The second switch is coupled between the output node and a ground voltage, and selectively closes and opens according to the second control signal. The output node is used to output an output clock.