SR Latch Inverter Loop With PFET Control for Faster State Changes
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Solution Overview
Problem
SR latch circuits experience input-to-output propagation delays due to the nature of logic gates, which can result in inefficiencies as the output does not change instantaneously in response to control input signals, particularly evident in SR NAND latch signals that incur two propagation delays through cross-coupled NAND gates.
Innovation Solution
The implementation of SR latch circuits with an inverter storage loop and a set of PFETs or NFETs for control circuitry, where PFETs and NFETs are connected to nodes of the inverter storage loop, allowing control inputs to manage state information storage, reducing propagation delays by enabling single input-to-output delays per state change.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cross-coupled NAND gates are used to implement SR latch, then the latch can store state information, but the input-to-output propagation delay increases due to two delays through the gates
Solution Approach 1:
The patent segments the latch functionality into separate components: one dedicated to state storage (cross-coupled inverters) and another to control (NAND gates with direct output connections). This segmentation allows the storage function to be isolated from the control logic, eliminating the propagation delay penalty that would otherwise affect state transitions.
Solution Approach 2:
The patent introduces an intermediary structure where the control NAND gates connect directly to the output nodes without passing through the entire inverter loop. This intermediary connection path provides a direct route for control signals to affect outputs, reducing the number of logic stages traversed and minimizing propagation delay.
2Ease of operation
If logic gates are used in SR latch circuit, then the circuit can control state information, but the output does not change instantaneously in response to control input signals
Solution Approach 1:
The control NAND gates are positioned and connected such that their output is directly available at the latch output nodes. This preliminary arrangement ensures that when control inputs change state, the effect is immediately reflected at the outputs without waiting for signals to propagate through the entire inverter loop, thereby improving response speed while maintaining control capability.
3Reliability
If multiple propagation delays are incurred in SR latch, then the circuit structure is more robust, but the efficiency of state changes decreases
Solution Approach 1:
The patent creates a dynamic structure where the control path can operate independently of the full storage loop. The control NAND gates can rapidly switch the output state without being constrained by the slower inverter loop propagation, enabling efficient state changes while the cross-coupled inverters maintain circuit robustness and stable state retention.
Data Source
AI summary
Examples disclosed herein relate to set-reset (SR) latch circuits and methods for manufacturing the same. In some of the disclosed examples, a SR latch circuit includes an inverter storage loop for storing state information and a set of p-channel field-effect transistors (PFETs) for control circuitry. The PFETs may include first and second PFETs connected to a first node of the inverter storage loop, and third and fourth PFETs connected to a second node of the inverter storage loop. Gate terminals of the first and fourth PFETs may be connected to a first control input, and gate terminals of the second and third PFETs may be connected to a second control input.