Model-Based SRAF Placement for Lithography Process Margins
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Solution Overview
Problem
The semiconductor industry faces challenges in maintaining adequate process margins in sub-wavelength lithography due to decreasing feature sizes, which require more aggressive reduction of the k1 factor, leading to increased complexity and cost in mask formation and manufacturing.
Innovation Solution
A model-based approach for determining the optimal placement of main features in the mask layout using iterative simulation and the generation of Layout Guidance Maps (LGMs) to enhance imaging performance, allowing for systematic optimization of feature placement and improved process windows.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes are decreased to continue scaling, then device density and functionality are improved, but process margins in lithography deteriorate
Solution Approach 1:
The patent applies preliminary action by performing model-based lithography guided layout design before the actual lithography process. The system iteratively simulates different layout configurations and selects the optimal one in advance, ensuring that the mask pattern is pre-optimized for the specific lithography process conditions. This preliminary optimization of the layout design ensures that when the actual lithography is performed, the process margins are maximized even at reduced feature sizes.
Solution Approach 2:
The patent implements feedback through iterative simulation and verification. The system simulates the lithography process for different layout configurations, compares the simulated results against the desired design rules, and uses this feedback to refine the layout. This closed-loop approach allows continuous improvement of the layout design based on actual lithography process characteristics, ensuring optimal process margins are achieved.
2Measurement precision
If k1 factor is reduced to maintain resolution at smaller features, then imaging capability is improved, but mask formation complexity and cost increase
Solution Approach 1:
The patent applies parameter changes by optimizing the layout design parameters specifically for the lithography process. Instead of using standard CAD design rules, the system adjusts geometric parameters such as feature dimensions, spacing, and shapes based on the specific lithography process conditions (k1 factor, NA, wavelength). This targeted parameter optimization allows the mask pattern to be tailored to achieve optimal imaging performance at the desired k1 factor without requiring excessive complexity in mask formation.
Solution Approach 2:
The patent implements local quality by applying different design rules and optimization strategies to different regions of the mask pattern. The system identifies critical features and regions that are most sensitive to lithography process variations and applies enhanced optimization locally to those areas. This localized approach allows the mask design to achieve optimal imaging capability in critical regions without uniformly increasing complexity across the entire mask.
3Manufacturing precision
If traditional Resolution Enhancement Techniques are applied extensively, then imaging performance is improved, but manufacturing cost increases
Solution Approach 1:
The patent applies preliminary action by incorporating lithography process optimization directly into the layout design phase. Instead of applying RET techniques as separate post-processing steps, the system integrates the optimization into the initial design and iterative refinement process. This preliminary incorporation of process considerations eliminates the need for extensive separate RET operations, reducing manufacturing cost while maintaining imaging performance.
Solution Approach 2:
The patent merges the layout design process with the lithography process optimization. Rather than treating RET techniques as separate, additive steps, the system combines layout design and process optimization into a unified iterative process. The model-based guided layout design inherently incorporates the necessary corrections and optimizations, merging multiple functions into a single integrated process that is more cost-effective than traditional separate RET operations.
Data Source
AI summary
Methods are disclosed to create efficient model-based Sub-Resolution Assist Features (MB-SRAF). An SRAF guidance map is created, where each design target edge location votes for a given field point on whether a single-pixel SRAF placed on this field point would improve or degrade the aerial image over the process window. In one embodiment, the SRAF guidance map is used to determine SRAF placement rules and/or to fine-tune already-placed SRAFs. The SRAF guidance map can be used directly to place SRAFs in a mask layout. Mask layout data including SRAFs may be generated, wherein the SRAFs are placed according to the SRAF guidance map. The SRAF guidance map can comprise an image in which each pixel value indicates whether the pixel would contribute positively to edge behavior of features in the mask layout if the pixel is included as part of a sub-resolution assist feature.