SRAM Contact Layout Using 3D Segmented Contacts for Lower Resistance
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Solution Overview
Problem
The challenge in semiconductor manufacturing is to reduce contact resistance in SRAM cells as they scale down, which affects device performance, and existing techniques have not been entirely satisfactory in optimizing SRAM performance and design requirements.
Innovation Solution
The proposed solution involves optimizing the layout and structure of SRAM cells by modifying the contact elements, specifically the source/drain contacts, to reduce resistance, including the use of FinFET devices and high-K/metal gate stacks, and modifying the layout to improve interconnection efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If SRAM cell dimensions are scaled down to improve production efficiency and lower costs, then manufacturing productivity increases, but contact resistance increases affecting device performance
Solution Approach 1:
The contact structure is divided into multiple segments: a first contact portion extending from the source/drain region through the interlayer dielectric, and a second contact portion extending from the first contact portion through an additional interlayer dielectric layer. This segmentation allows each contact segment to be optimized independently for its specific function and location, reducing overall contact resistance while maintaining scaled-down cell dimensions
Solution Approach 2:
The contact structure transitions from a single-plane contact to a multi-layer, three-dimensional contact architecture. The first and second contact portions are positioned at different vertical levels through multiple interlayer dielectric layers, creating a distributed contact path that reduces resistance without increasing lateral footprint, thus maintaining scaled-down cell area
2Area of moving object
If SRAM cell dimensions are scaled down, then device size decreases, but contact resistance increases affecting device performance
Solution Approach 1:
The contact structure utilizes the vertical dimension by extending contact portions through multiple interlayer dielectric layers at different heights. This three-dimensional contact architecture reduces contact resistance by providing multiple contact interfaces and increasing the effective contact area in the vertical direction, without increasing the lateral area of the SRAM cell
Solution Approach 2:
The contact is segmented into first and second contact portions positioned at different vertical levels. Each segment can be independently optimized for its specific location and function, with the first contact portion providing initial electrical connection and the second contact portion providing additional contact area and lower resistance path, all within the scaled-down cell footprint
Data Source
AI summary
An SRAM device and method of forming include pass gate (PG), pull-down (PD), and pull-up (PU) transistors. A first gate line of the PG and a second gate line of the PD and the PU extend in a first direction. A common source/drain of the PG, PD, and PU transistors interposes the first and second gate lines and another source/drain of the PG transistor. A first contact extends from the common source/drain and a second contact extends from the another source/drain. A third contact is disposed above the second contact with a first width in the first direction and a first length in a second direction, first length being greater than the first width.