SRAM In-Memory Computing With 8T Cells and Dedicated 2T Read Paths
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Solution Overview
Problem
Current in-memory computing approaches, such as using six transistor (6T) and eight transistor (8T) memory cells, face challenges like accidental writes, stability issues, and the need for separate logic dies, which increase costs and reduce efficiency in neural networks and ASICs operating at low voltage ranges.
Innovation Solution
A circuit and method utilizing an eight transistor (8T) memory cell structure with a six transistor (6T) memory cell in read/write mode and a two transistor (2T) memory cell with a dedicated read port, integrated with a bi-directional sense amplifier and write driver, and a configurable data path unit to perform arithmetic logical operations in parallel, reducing memory bank restrictions and enabling high-bandwidth read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a six transistor (6T) memory cell is used for in-memory computing, then computing functionality is integrated into memory, but accidental writes occur and stability issues arise when both wordlines are activated simultaneously
Solution Approach 1:
The patent divides the memory cell into two separate functional units: a 6T memory cell for write operations and a dedicated 2T memory cell for read operations. This segmentation eliminates the conflict between read and write operations that causes accidental writes and instability in conventional 6T cells, while preserving the in-memory computing capability through the integrated data path circuit.
2Adaptability or versatility
If a conventional eight transistor (8T) memory cell is used for logic operations, then logic functionality is integrated into memory, but inverter trip points vary with different processes, voltages, and temperatures making detection difficult
Solution Approach 1:
The patent extracts the inverter-based logic detection mechanism from the conventional 8T cell and replaces it with a dedicated 2T memory cell read mechanism. This extraction eliminates the PVT sensitivity of inverter trip points, as the 2T cell uses a simpler, more stable read mechanism that does not rely on inverter characteristics, while still enabling logic operations through the integrated data path.
3Adaptability or versatility
If separate logic dies are used to augment DRAM for computing, then computing capability is added, but substantial cost increases and the approach does not reduce the separation between memory and computing
Solution Approach 1:
The patent merges the data path circuit directly into the memory array structure, combining memory storage and computing logic into a single integrated unit. This eliminates the need for separate logic dies augmenting DRAM, reduces system complexity, and maintains the close integration of memory and computing functions while enabling in-memory computing capabilities.
4Adaptability or versatility
If longer wordline pulse width is used for NOR operation in 8T cells, then detection of logic operations is enabled, but reading cases like '01' or '10' on wordlines becomes difficult
Solution Approach 1:
The patent introduces a dedicated 2T memory cell as an intermediary structure that simplifies the read operation. Instead of relying on complex wordline pulse width variations to detect logic operations, the 2T cell provides a clean, dedicated read path that makes all read cases (including '01' and '10') equally easy to detect, while the data path circuit handles the logic operation detection.
Data Source
AI summary
The present disclosure relates to in-memory computing using a static random access memory (SRAM). In particular, the present disclosure relates to a structure including a memory configured to store a first word and a second word, the memory further includes a configurable data path circuit, and the configured data path circuit is configured to perform an arithmetic logical operation based on the first word and the second word in parallel.