SRAM Cell Layout Using Active Bridges and Buried Oxide
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Solution Overview
Problem
The challenge in miniaturizing SRAM cells using a CMOS process is due to the difficulty in reducing the size of SRAM cells, as the margins between contacts and metal interconnects decrease, making it hard to scale down the cell size effectively.
Innovation Solution
The integrated circuit design includes a configuration with multiple NMOS and PMOS regions, active bridges, and a buried oxide layer to enhance integration density, allowing for reduced cell size by eliminating the need for additional contacts and improving interconnect design freedom.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If six transistors are arranged in a single SRAM cell using CMOS process, then the SRAM cell can be constructed with standard CMOS technology, but the size of the SRAM cell cannot be reduced effectively due to decreasing margins between contacts and metal interconnects
Solution Approach 1:
The patent divides the SRAM cell into separate NMOS and PMOS regions rather than arranging all six transistors in a single compact cell. This segmentation allows independent optimization of each region and reduces the overall cell footprint by eliminating the need for complex interconnect structures within a unified cell layout.
Solution Approach 2:
The patent transitions from a planar two-dimensional arrangement of transistors within a single cell to a three-dimensional distributed structure where NMOS and PMOS regions are separated and connected through vertical interconnects. This dimensional change enables reduced cell area by utilizing vertical space for connections rather than requiring lateral routing space.
2Area of moving object
If continuous scaling down process is applied to reduce SRAM cell size, then miniaturization is achieved, but margins between contacts and metal interconnects decrease making further miniaturization challenging
Solution Approach 1:
The patent merges the source/drain regions of transistors within the same type (NMOS or PMOS) into shared active regions. For example, the source/drain of the first pass transistor and the source/drain of the first pull-down transistor share a common active region, eliminating the need for separate contacts and reducing overall cell area while maintaining adequate manufacturing margins.
Solution Approach 2:
The active regions serve multiple functions: they act as source/drain for multiple transistors simultaneously, eliminate the need for separate contact structures, and provide electrical interconnection between transistors. This multi-functionality reduces the number of discrete components and simplifies the interconnect structure, enabling further scaling.
3Reliability
If additional contacts and metal interconnects are used to connect transistors, then transistor connectivity is ensured, but the SRAM cell size increases and integration density decreases
Solution Approach 1:
The patent extracts and eliminates unnecessary contact structures and metal interconnects by merging active regions. The shared active regions directly provide electrical connectivity between transistors without requiring additional contact holes or metal routing layers, thereby reducing cell area and increasing integration density while maintaining reliable transistor connections.
Data Source
AI summary
The present disclosure refers to integrated circuits and static random access memories. In an embodiment, an integrated circuit includes a first n-type metal oxide semiconductor (NMOS) region, a second NMOS region, a first p-type MOS (PMOS) region between the first NMOS region and the second NMOS region, a second PMOS region between the first PMOS region and the second NMOS region, and a first active bridge extending in a first direction and coupling the first NMOS region to the first PMOS region. A level of the first active bridge matches levels of the first electrode of the first pass transistor, the second electrode of the first pass transistor, the first electrode of the first pull-down transistor, the second electrode of the first pull-down transistor, the first electrode of the first pull-up transistor, and the second electrode of the first pull-up transistor.