SRAM Block With Integrated Adder For Radar Sensor Power Reduction
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Solution Overview
Problem
The existing static random access memory (SRAM) blocks in lidar and radar sensor ASICs face challenges with high power consumption and heat generation due to the need to read and write large amounts of data quickly, leading to inefficient data processing and excessive energy usage.
Innovation Solution
Integrating an adder within the SRAM block between the data input and the read/write module allows for combined read and write operations, reducing the number of memory accesses and only processing changed data, thereby lowering energy consumption and heat generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If data processing is performed outside the SRAM block by reading original data, processing externally, and writing back results in separate cycles, then data processing capability is maintained, but power consumption increases and processing efficiency decreases
Solution Approach 1:
The patent merges the data processing function (adder) with the storage function (SRAM block) by integrating the adder internally. This allows read, process, and write operations to be combined into a single memory cycle, eliminating the need for separate read and write cycles. The adder is positioned between the data input and the read/write module to enable direct processing of retrieved data before rewriting, thereby reducing power consumption while maintaining or improving processing efficiency.
2Power
If multiple SRAM blocks are accessed in parallel to handle large data volumes, then data processing capacity is sufficient, but heat generation and power consumption increase significantly
Solution Approach 1:
By integrating the adder into the SRAM block, the patent enables combined read-process-write operations within a single memory cycle. This reduces the total number of memory accesses required across multiple SRAM blocks, thereby lowering the aggregate power consumption and heat generation while maintaining the necessary processing capacity for handling large data volumes from lidar and radar sensors.
3Speed
If the memory clock frequency is increased to process data faster, then data processing speed improves, but power consumption and heat generation increase
Solution Approach 1:
The patent combines multiple operations (read, add, write) into a single memory cycle, which reduces the total number of cycles required for data processing. This allows the memory clock frequency to be reduced while maintaining the same overall processing throughput, thereby lowering energy consumption and heat generation without sacrificing data processing speed.
Data Source
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AI summary
The invention relates to a static direct access memory block (20), in particular for a receiving sensor, comprising a memory cell field (21), a row address decoder (22), a column data multiplexer (23), a read and write module (24) comprising a read amplifier and a write driver, a control logic unit (25), a data input (26) and a data output (27). The static direct access memory block (20) has internal memory clocking. According to the invention, at least one adder (28) for adding input data entered through the data input (26) is integrated into the static direct access memory block (20), wherein the at least one adder (28) is arranged between the data input (26) and the read and write module (24). As a result, the read and write operations can be optimised and thus power consumption can be reduced. The invention also relates to a receiving sensor, in particular for a radar or lidar system, comprising an application-specific integrated circuit. The application-specific integrated circuit comprises at least one static direct access memory block (20) according to the invention.