SRAM Aging Sensor Dynamic Voltage Scaling
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Solution Overview
Problem
In SRAM caches, the degradation of read minimum power supply voltage VDDMIN over time due to aging stress poses a challenge, leading to overly pessimistic design margins and increased power consumption, necessitating a method to monitor and adjust for aging without occupying significant circuit area.
Innovation Solution
An aging sensor using an array of sensor SRAM cells with adjustable wordline overdrive voltage (VWLOD) is employed to dynamically monitor and calibrate the minimum power supply voltage (VDDMIN), allowing for precise adjustment of VDDMIN to match or exceed that of active SRAM cells, thereby reducing unnecessary guard bands and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a large NBTI voltage margin is set to account for worst-case aging stress, then reliability is improved, but power consumption increases and circuit area is wasted
Solution Approach 1:
The patent implements dynamic adjustment of the read voltage margin based on actual aging conditions. Instead of using a fixed conservative margin, the system continuously monitors aging through sensor bitcells and adjusts the wordline overdrive voltage (VWLOD) accordingly. This allows the system to maintain reliability while optimizing power consumption by using only the necessary margin at any given time.
Solution Approach 2:
The patent employs a feedback mechanism where aging sensor bitcells monitor the actual aging state of the SRAM array and provide information to adjust the read voltage margin. The system measures aging through comparative readings between sensor and active bitcells, then uses this feedback to dynamically tune VWLOD, ensuring reliability is maintained at the minimum necessary level rather than using excessive conservative margins.
2Reliability
If a large NBTI voltage margin is set to account for worst-case aging stress, then reliability is improved, but circuit area is increased
Solution Approach 1:
The patent extracts the aging monitoring function into separate sensor bitcells that are distinct from the active SRAM array. These sensor bitcells are dedicated to measuring aging and do not participate in normal data storage operations. This separation allows the system to maintain a compact active array while using a minimal overhead of sensor cells for reliability monitoring and dynamic margin adjustment.
Solution Approach 2:
The patent uses sensor bitcells that are copies of the active SRAM bitcell structure, containing the same PMOS and NMOS transistors configured identically. These copied structures undergo the same aging processes but are dedicated to monitoring purposes. By using identical copies, the system can accurately measure aging without requiring complex or larger sensor structures.
3Reliability
If conservative flat guard band is used for VDDMIN, then reliability is improved, but adaptability deteriorates
Solution Approach 1:
The patent transitions from a static conservative guard band to a dynamic adaptive margin system. The read voltage margin (VWLOD) is continuously adjusted based on real-time aging measurements from sensor bitcells. This allows the system to adapt to actual aging conditions, using larger margins only when necessary and smaller margins when aging is minimal, thereby improving both reliability and adaptability.
Solution Approach 2:
The patent changes the voltage parameter VWLOD dynamically based on aging conditions. Instead of fixing the read voltage margin at a conservative value, the system adjusts VWLOD as a variable parameter according to the measured aging state. This parameter change enables the system to adapt to different aging stages and operating conditions, optimizing both reliability and voltage efficiency.
Data Source
AI summary
In a static random access memory (SRAM), such as an SRAM cache in a processor or system-on-a-chip (SoC) device, an aging sensor is provided for testing degradation of SRAM cells comprising p-channel metal oxide semiconductor (PMOS) transistors. The minimum power supply voltage VDDMIN for the SRAM may be dynamically scaled up as the SRAM ages by performing read tests with and without the wordline overdrive voltage VWLOD.