SRAM Compute Array Modulating Wordline Voltage for Analog MAC
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Solution Overview
Problem
Current SRAM-based process in memory systems are limited by binary storage and the overhead of multi-bit analog-to-digital conversion, making them unsuitable for high-precision multiply-accumulate operations required in solving partial differential equations, which demand iterative multi-bit operations and high numerical precision.
Innovation Solution
A system comprising an array of SRAM cells interconnected by wordlines and bitlines, where memory cells store multibit multiplicands and output products proportional to the significance of the bit stored, with a driver circuit and input switches to modulate voltages and activate wordlines based on multiplier values, supporting low-cost analog-to-digital converters for efficient digitization of outputs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If SRAM-based PIM designs use binary storage and multi-bit ADCs, then measurement precision is improved, but device complexity and cost increase
Solution Approach 1:
The patent segments the multiply-accumulate operation into two phases: analog multiplication phase where products are generated in analog form directly in memory, and digital conversion phase where only final sums are converted by ADCs. This segmentation allows most operations to remain in the analog domain, reducing ADC requirements from multi-bit to 1-bit, thereby reducing device complexity while maintaining measurement precision.
Solution Approach 2:
The patent introduces an intermediary mechanism where the SRAM cell currents serve as analog multipliers that directly produce product values on bitlines. These analog products are summed in the analog domain before undergoing a single 1-bit ADC conversion. This intermediary analog computation stage eliminates the need for multiple ADCs, reducing complexity while preserving precision through the analog summation process.
2Device complexity
If SRAM-based PIM designs quantize outputs to 1 b or use cone structures, then device complexity is reduced, but adaptability for iterative multi-bit operations is lost
Solution Approach 1:
The patent implements dynamic operation modes that allow the system to adapt between different computational requirements. The SRAM array can operate in analog mode for PDE solving requiring multi-bit precision, or be configured for other applications. The driver circuit and input switches dynamically control the operation mode, enabling the system to maintain adaptability for iterative multi-bit operations while using simple 1-bit ADCs through dynamic reconfiguration rather than fixed quantization.
3Productivity
If hardware PDE solvers scale up to support practical problems, then productivity is improved, but device complexity increases due to memory bandwidth requirements
Solution Approach 1:
The patent enables the memory array to perform compute operations self-service within its structure. Multiply-accumulate operations are executed directly in the SRAM array using the existing memory cells, wordlines, and bitlines as computational elements. This eliminates the need for separate high-bandwidth memory interfaces and compute units, as the memory structure itself provides the computational capability, thereby improving productivity without increasing memory bandwidth infrastructure complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables efficient multiply-accumulate operations on multibit multiplicands and multipliers, achieving high performance and energy efficiency in solving partial differential equations by reducing the need for multi-bit ADCs and supporting sufficient output digitization, thereby speeding up convergence and improving precision.
Implementation Method 1
A driver circuit is electrically connected to each wordline in a given group of memory cells and operates to drive the wordlines with a set of voltages, where magnitude of the voltage produces a cell discharging current that is proportional to significance of bit stored in the corresponding memory cell
Implementation Method 2
The SRAM cells' currents in discharging the bitlines represent the products, and the total current on each bitline represents the sum of products
Data Source
AI summary
Many signal processing, machine learning and scientific computing applications require a large number of multiply-accumulate (MAC) operations. This type of operation is demanding in both computation and memory. Process in memory has been proposed as a new technique that computes directly on a large array of data in place, to eliminate expensive data movement overhead. To enable parallel multi-bit MAC operations, both width- and level-modulating memory word lines are applied. To improve performance and provide tolerance against process-voltage-temperature variations, a delay-locked loop is used to generate fine unit pulses for driving memory word lines and a dual-ramp Single-slope ADC is used to convert bit line outputs. The concept is prototyped in a 180 nm CMOS test chip made of four 320×64 compute-SRAMs, each supporting 128× parallel 5 b×5 b MACs with 32 5 b output ADCs and consuming 16.6 mW at 200 MHz.