SRAM At-Speed Testing via Multi-Stage Flip-Flop Pipeline
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current testing methods for complex integrated circuits, particularly static random access memory (SRAM), are inadequate as they do not effectively test internal structures at the operating clock speed, leading to incomplete defect detection due to slow testing speeds and difficulties in applying multiple cycle inputs.
Innovation Solution
A multi-stage pipeline of flip-flops is used to provide a series of test inputs at the core clock speed of the SRAM, allowing for at-speed testing by dynamically controlling the timing of test input signals, thereby changing internal states of the SRAM as if it were under normal operation conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a single input is applied before testing is paused to load the next value, then the testing tool can detect certain types of defects, but the testing speed is slow and does not reach operating clock speed
Solution Approach 1:
The patent pre-calculates and stores multiple cycle test inputs in a memory structure before testing begins. This preliminary preparation allows the testing tool to feed multiple inputs continuously to the SRAM without pausing to reload, enabling at-speed testing while maintaining comprehensive defect detection capability
Solution Approach 2:
The patent introduces an intermediate memory structure that stores pre-computed test inputs. This intermediary buffer decouples the slow test generation process from the fast testing process, allowing the SRAM to be tested at its full operating clock speed while the testing tool operates at its slower pace of preparing test patterns
2Reliability
If multiple cycle inputs are used for testing SRAM, then comprehensive defect detection is achieved, but it is difficult to back-compute and apply at core clock speed
Solution Approach 1:
The patent pre-computes multiple cycle test inputs offline and stores them in a memory structure before testing. This eliminates the complexity of real-time back-computation during at-speed testing, while still achieving comprehensive defect detection through the use of multi-cycle test patterns
Solution Approach 2:
The patent creates a copy of the test input sequence in a memory structure that can be rapidly accessed during testing. This copied test pattern allows the SRAM to be tested with complex multi-cycle inputs at full clock speed without requiring the testing tool to perform complex real-time computations
Data Source
AI summary
Systems, methods, and other embodiments associated with at-speed testing of static random access memory (SRAM) are described. In one embodiment, a method includes loading, into a multi-stage pipeline of memory devices, a control pattern for testing a static random access memory (SRAM). The SRAM is tested by generating a test input that is based, at least in part, on the control pattern from the multi-stage pipeline of flip-flops. The test input is provided to the SRAM over a series of clock cycles that are at a core clock speed of the SRAM.