Five-Transistor SRAM Cell with Auxiliary Access for Low-Voltage Write
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Solution Overview
Problem
Conventional portless, five-transistor SRAM memory cells face challenges in low power supply voltage environments, such as 45 nanometre technologies, where maintaining sufficient voltage differences between bit lines for write and read operations without affecting stability is difficult, especially in advanced technologies.
Innovation Solution
Incorporating an additional memory cell connected to the bit lines with controllable access means and control signals to manage the access transistor states, allowing for read and write operations without the need for a current amplifier, thus avoiding voltage offset issues and reducing dynamic consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional portless, five-transistor SRAM memory cells are used in low power supply voltage environments, then device complexity is reduced, but voltage difference between bit lines becomes insufficient for reliable write and read operations
Solution Approach 1:
The patent applies preliminary action by precharging the bit lines to the power supply voltage before write operations. This precharging ensures that sufficient voltage difference is available when the access transistor is activated, enabling reliable write operations even in low power supply voltage environments without requiring additional circuit complexity
Solution Approach 2:
The patent changes the operating parameters by using controlled voltage levels on the access transistor gate. By applying a gate voltage higher than the power supply voltage during write operations, the access transistor conductance is enhanced, enabling sufficient current flow and voltage difference generation despite the low power supply voltage constraint
2Reliability
If bit lines are precharged to power supply voltage for each write operation, then write reliability is improved, but dynamic power consumption increases
Solution Approach 1:
The patent applies local quality by selectively precharging only the bit lines that are required for the specific write operation, rather than precharging all bit lines in the memory array. This localized approach reduces the capacitive load and consequently reduces the dynamic power consumption while maintaining write reliability
Solution Approach 2:
The patent uses periodic action by implementing controlled precharging cycles that are synchronized with write operations. The bit lines are precharged only when needed, and the access transistor is activated in a periodic manner according to the write operation requirements, reducing unnecessary charging and discharging cycles that would increase power consumption
3Reliability
If access transistor gate voltage is increased above power supply voltage, then write capability is improved, but device complexity and power management complexity increase
Solution Approach 1:
The patent uses an intermediary approach by introducing a control signal that mediates between the power supply voltage and the access transistor gate. This control signal, generated by existing control logic, temporarily elevates the gate voltage above the power supply voltage during write operations without requiring complex dedicated voltage generation circuitry, thus improving write capability while limiting the increase in device complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient read and write operations in low power supply voltage environments by using the same circuit for both operations, reducing dynamic consumption and eliminating the need for bit line charging and discharging during write operations, while maintaining data stability.
Implementation Method 1
When the access transistor AXS is opened (blocked or OFF), the cell CEL is stable and the datum is kept in that cell as long as the cell remains powered by the power supply voltage. When the access transistor AXS is closed (passing or ON), a current flows from the node T or F presenting the logic value 1 to the node F or T presenting the logic value 0.
Implementation Method 2
To write a datum into the cell CEL, the two bit lines are first of all precharged at the power supply voltage, the transistor AXS is closed and the voltage of one of the bit lines is made to drop depending on whether the desire is to write a 1 or a 0, so as to provoke a voltage difference between the nodes T and F of the cell.
Implementation Method 3
To read the datum from the cell CEL, the transistor AXS is closed. A current difference is then created between the two bit lines, the sign of which depends on the logic value of the stored datum. This current difference is amplified conventionally in a current amplifier located at the bottom of the column of the memory plane containing the cell, and the datum is thus read.
Data Source
AI summary
At the bottom of a column (COLi) of memory cells (CEL) of the SRAM type with five portless transistors, there is placed an additional cell (CLS), with a structure identical to the cells (CEL), which makes it possible to write and read a datum in a memory cell (CEL) of the column without using a read amplifier.