SRAM Bitcell Screening via Back-Bias Voltage Drift
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Solution Overview
Problem
Semiconductor manufacturers face challenges in ensuring the long-term stability of SRAM memory cells due to negative bias temperature instability (NBTI) and other phenomena that cause transistor threshold voltage changes, leading to potential device failure, which can result in yield loss and liability issues during burn-in testing.
Innovation Solution
A method is introduced to modify the reliability characteristics of SRAM bitcells by altering the bias voltage of MOS transistors, allowing for the identification and replacement of marginal bitcells before they fail, using electrical connections to n-wells of pMOS load transistors and applying test voltages different from the operating bias to simulate expected drift over the operational lifetime.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If burn-in testing is performed to screen for SRAM failures, then customer reliability is protected, but manufacturing yield decreases due to premature failures during testing
Solution Approach 1:
The patent applies preliminary action by performing back-bias testing at time zero (before burn-in) to identify and replace marginal bitcells that are prone to premature failure. This advance screening allows weak cells to be replaced with redundant cells before the burn-in process, so they don't fail during testing and reduce yield loss while still protecting customer reliability.
Solution Approach 2:
The patent applies preliminary anti-action by using back-bias to induce threshold voltage shifts that simulate end-of-life conditions, thereby identifying weak bitcells before they fail. This preliminary countermeasure allows replacement of vulnerable cells with redundant ones, preventing the harmful effect of premature failures during burn-in testing.
2Difficulty of detecting and measuring
If burn-in conditions are intensified to accelerate failure modes, then detection capability improves, but device stress increases causing additional failures
Solution Approach 1:
The patent applies parameter changes by modifying the bias voltage parameter (applying back-bias to the well) to induce threshold voltage shifts that simulate end-of-life conditions. This allows detection of marginal bitcells under controlled electrical stress rather than intense thermal and electrical stress, improving detection capability while reducing harmful device stress.
3Reliability
If threshold voltage drift is monitored to identify marginal bitcells, then reliability screening improves, but testing complexity increases
Solution Approach 1:
The patent applies copying by using the back-bias technique to create a test condition that replicates end-of-life threshold voltage drift. Instead of complex long-term reliability testing, a simplified test structure with back-bias application copies the essential failure mechanism, enabling reliable screening with reduced testing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the risk of premature SRAM failure by identifying and replacing weak bitcells, thereby enhancing product yield and reducing the likelihood of customer-facing failures, while maintaining the design operating voltage and avoiding unnecessary cost increases.
Implementation Method 1
Negative bias temperature instability (NBTI), defects, or other phenomena may be manifested as a transistor threshold voltage (Vt) change over time
Data Source
AI summary
A method of manufacturing a semiconductor device includes providing an electrical connection to a well of a MOS transistor of a static random access memory (SRAM) cell. A predetermined voltage is applied to the well using the connection to cause a threshold voltage (Vt) of said transistor to change. The change is employed to identify a reliability characteristic of the semiconductor device. An SRAM parameter is altered to modify the reliability characteristic.


