SRAM Cell Back-Gate Biasing for Variable Toggle Threshold
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing SRAM circuits face challenges in reducing circuit area while maintaining efficient transistor usage, often requiring asymmetric transistor sizing and complex biasing conditions, which can lead to increased leakage.
Innovation Solution
The implementation of SRAM cells with multiple transistors featuring both primary and secondary gates, allowing for concurrent biasing through a secondary gate node, enabling variable toggle threshold voltage (Vtth) adjustment, and utilizing a fully depleted semiconductor-on-insulator technology to facilitate a 5T SRAM cell design with a single bitline per column.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the number of transistors per SRAM cell is reduced to decrease area, then area is improved, but leakage increases and complex biasing conditions are required
Solution Approach 1:
The patent applies parameter changes by introducing a variable toggle threshold voltage (Vtth) that can be dynamically adjusted based on operational mode. By changing the Vtth parameter, the SRAM cell can optimize its performance for either read or write operations, enabling reduced transistor count while maintaining low leakage through appropriate threshold voltage selection for each operational state
Solution Approach 2:
The patent implements dynamics by making the toggle threshold voltage adjustable and mode-dependent. The SRAM cell transitions between different Vtth states depending on whether it is performing read or write operations, allowing the cell to adapt its electrical characteristics dynamically to minimize leakage while maintaining functionality with fewer transistors
2Area of stationary object
If asymmetric transistor sizing is used to reduce SRAM cell area, then area is improved, but device complexity increases
Solution Approach 1:
The patent strategically applies asymmetry only where necessary - in the variable toggle threshold voltage mechanism - while maintaining symmetry in the core transistor pair structure. This selective asymmetry approach reduces overall device complexity compared to fully asymmetric designs, as the symmetric transistor pairing simplifies layout and manufacturing while the asymmetric Vtth control provides the area reduction benefit
3Area of stationary object
If complex biasing conditions are implemented to reduce SRAM cell area, then area is improved, but device complexity increases
Solution Approach 1:
The patent applies universality by designing a variable Vtth mechanism that serves multiple functions: it enables area reduction through fewer transistors, maintains low leakage through appropriate threshold selection, and simplifies biasing requirements by providing a unified control approach for different operational modes. This multi-functional Vtth control eliminates the need for separate complex biasing circuits that would otherwise be required
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces SRAM circuit area without asymmetric transistor sizing, minimizing leakage and enhancing flexibility in design by allowing for symmetric transistors, while maintaining efficient switching speeds and data integrity during read and write operations.
Implementation Method 1
The secondary gate node can be electrically connected to the secondary gates of all of the multiple transistors within the memory cell to enable concurrent biasing of the secondary gates
Implementation Method 2
utilizing a fully depleted semiconductor-on-insulator technology to facilitate a 5T SRAM cell design
Data Source
AI summary
A static random access memory (SRAM) cell includes P-type and N-type transistors having secondary gates. A node connected to all secondary gates receives a write enable signal (WEN). A low WEN forward biases the P-type transistors and increases the toggle threshold voltage (Vtth) of the SRAM cell to avoid data switching during a read. A high WEN forward biases the N-type transistors and decreases Vtth during a write. The SRAM cell can be implemented using a fully depleted semiconductor-on-insulator technology, where the secondary gates include corresponding portions of a well region below. In this case, an array of SRAM cells can be above a single well region. Alternatively, the array can be sectioned into sub-arrays above different well regions and a decoder can output sub-array-specific WENs to the different well regions (e.g., with only one WEN being high at a given time to reduce capacitance).