SRAM Memory Structure With Back-Side Routing for GAA Scaling
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Solution Overview
Problem
As integrated circuit technologies progress towards smaller technology nodes, gate-all-around (GAA) transistors in memory devices face challenges with interconnection routing, leading to increased routing resources and impact on cell scaling and performance.
Innovation Solution
The implementation of an array of static random-access memory (SRAM) cells with bit-line and bit-line-bar conductors under the SRAM cells, utilizing back-side interconnection structures to reduce routing complexity and improve cell performance, combined with gate-all-around transistors that allow better gate control and improved scaling capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If traditional front-side interconnection routing is used for GAA transistor memory arrays, then routing connectivity is achieved, but routing resource consumption increases and cell scaling is impacted
Solution Approach 1:
The patent implements back-side interconnection structures that route bit-line and bit-line-bar conductors through the substrate beneath the SRAM cells, transitioning the routing from a two-dimensional planar layout to a three-dimensional configuration. This dimensional change allows routing resources to be separated from the cell plane, reducing routing complexity while preserving cell scaling benefits.
2Productivity
If GAA transistors are scaled down to reduce chip footprint, then functional density increases, but interconnection routing becomes more complex and impacts cell performance
Solution Approach 1:
The patent segments the interconnection system into front-side components (within the SRAM cell plane) and back-side components (beneath the cells). By dividing the routing function across these separate spatial domains, the complexity of interconnection is reduced while allowing continued scaling of the GAA transistors and increase in functional density.
3Reliability
If more routing resources are allocated for memory array interconnection, then connectivity is maintained, but cell scaling and performance are degraded
Solution Approach 1:
The substrate serves as an intermediary medium that carries the bit-line and bit-line-bar conductors beneath the SRAM cells. This intermediary routing path maintains necessary connectivity between memory cells while eliminating the need for excessive routing resources in the cell plane, thereby preserving cell scaling and performance.
Data Source
AI summary
A memory structure includes: a static random-access memory (SRAM) cell having a first pass-gate transistor, a second pass-gate transistor, a first pull-down transistor, and a second pull-down transistor; a bit-line conductor and a bit-line-bar conductor, the bit-line conductor being electrically connected to a bottom surface of a source/drain of the first pass-gate transistor and the bit-line-bar conductor being electrically connected to a bottom surface of a source/drain feature of the second pass-gate transistor; a first VSS conductor and a second VSS conductor, the first VSS conductor being electrically connected to an upper surface of a source/drain of the first pull-down transistor and the second VSS conductor being electrically connected to an upper surface of a source/drain of the second pull-down transistor; and a word-line conductor, the word-line conductor being electrically connected to gate electrodes of the first and second pass-gate transistors and being over the first and second VSS conductors.