SRAM Back-Side Bit-Line Layout for Lower Routing Capacitance
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Solution Overview
Problem
The scaling down of semiconductor integrated circuits (ICs) leads to challenges in SRAM bit-line routing due to narrower X-pitch dimensions, causing increased bit-line capacitance and complex metal layouts, which affects SRAM stability and efficiency.
Innovation Solution
Positioning low power rail Vss1, bit lines BL, and bit line bars BLB at the back-side of the wafer, reducing routing load and enhancing metal conductor performance by increasing metal width and spacing, while organizing word-line routing and pass gate device straps into groups to reduce capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If scaling down is applied to increase functional density, then production efficiency is improved and costs are lowered, but bit-line capacitance increases and routing becomes more complex
Solution Approach 1:
The patent introduces a third dimension by routing bit lines through vias from one metal layer to another, allowing bit lines to be positioned in metal layer M2 while word lines remain in metal layer M1. This vertical stacking approach resolves the routing complexity by utilizing the Z-dimension rather than attempting to route all lines in the same plane, thereby reducing capacitance and simplifying the two-dimensional layout.
2Manufacturing precision
If scaling down is applied to increase functional density, then smaller geometry is achieved, but bit-line capacitance increases affecting SRAM stability
Solution Approach 1:
By routing bit lines through vias to a higher metal layer (M2), the patent increases the physical spacing between bit lines and the channel, thereby reducing parasitic capacitance. This dimensional separation maintains SRAM stability even as horizontal dimensions are scaled down to achieve higher functional density.
3Device complexity
If traditional front-side routing is used, then layout is simpler, but metal conductor performance is reduced due to narrower width and increased spacing
Solution Approach 1:
The patent utilizes the vertical dimension by routing bit lines through vias to metal layer M2, where they can be made wider with greater spacing compared to the constrained M1 layer. This improves metal conductor performance by reducing resistance and capacitance, while the via structure manages the increased layout complexity.
Data Source
AI summary
A method includes forming a static random access memory (SRAM) array in a device layer, wherein the SRAM array comprises a first SRAM cell and a second SRAM cell adjacent to the first SRAM cell, and from a top view, the first and second SRAM cells are arranged in a first direction; forming a first word line over a front-side of the device layer and extending across the first and second SRAM cells in the first direction, wherein the first word line is electrically coupled to the first SRAM cell; forming a bit line and a bit line bar over a back-side of the device layer, wherein the first and second SRAM cells share the bit line and the bit line bar.