SRAM Cell Layout With Back-Side Bit-Line Routing
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Solution Overview
Problem
As integrated circuit technologies progress towards smaller technology nodes, gate-all-around (GAA) transistors in memory devices face challenges with interconnection routing, leading to increased routing resources and impact on cell scaling and performance, which existing technologies have not adequately addressed.
Innovation Solution
The implementation of an array of static random-access memory (SRAM) cells with bit-line conductors and bit-line-bar conductors under the SRAM cells, along with back-side interconnection structures, reduces routing complexity and improves cell performance by relocating some interconnection components from the front-side to the back-side of the transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If interconnection routing is implemented for memory arrays using GAA transistors, then circuit functionality is achieved, but routing resource consumption increases and cell scaling is impacted
Solution Approach 1:
The patent introduces back-side interconnection routing as a new dimension for signal transmission. Bit-line and bit-line-bar conductors are routed on the back-side of the memory array, separate from the front-side word-line routing. This spatial separation reduces routing resource conflicts and allows independent optimization of read and write pathways, thereby reducing overall routing complexity while maintaining full circuit functionality.
2Reliability
If more routing resources are allocated for memory array interconnection, then circuit performance is maintained, but cell scaling is hindered
Solution Approach 1:
The interconnection routing is segmented into front-side and back-side pathways. Word-lines are routed on the front-side while bit-lines and bit-line-bars are routed on the back-side. This segmentation allows each routing layer to be optimized independently for its specific function, reducing the total routing resources required per cell and enabling further cell scaling while maintaining circuit performance.
3Ease of manufacture
If traditional front-side interconnection is used, then manufacturing is simpler, but routing complexity increases
Solution Approach 1:
By utilizing the back-side of the substrate for interconnection routing, the patent adds a new dimensional space for wire routing. This approach maintains manufacturing simplicity by using standard thin-film deposition and patterning processes extended to the back-side, while dramatically reducing routing complexity through spatial separation of different signal types (word-lines on front-side, bit-lines on back-side).
Data Source
AI summary
A memory structure includes a static random access memory (SRAM) cell having a first pass-gate transistor and a second pass-gate transistor, a word-line conductor extending in a first direction, a first source/drain contact, a second source/drain contact, a bit-line conductor in a second direction, and a bit-line-bar conductor extending in the second direction. The second direction is perpendicular to the first direction. The word-line conductor is over and electrically connected to gate electrodes of the first pass-gate transistor and the second pass-gate transistor. The first source/drain contact is under and electrically connected to a source/drain feature of the first pass-gate transistor. The second source/drain contact is under and electrically connected to a source/drain feature of the second pass-gate transistor. The bit-line conductor is under and electrically connected to the first source/drain contact. The bit-line conductor is under and electrically connected to the second source/drain contact.