SRAM Cell Back-Side Butt Contact Routing for IR Drop Reduction
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Solution Overview
Problem
The increasing complexity and density of semiconductor integrated circuits (ICs) lead to higher power dissipation, which is not effectively addressed by existing technologies, resulting in inefficiencies in processing and manufacturing, particularly due to increased resistance and capacitance in metal lines.
Innovation Solution
The implementation of a metal line routing method that includes bit-line, bit-line-bar, and power supply voltage lines at the front-side M1 level, without word-lines, to reduce resistance and capacitance, and connects power supply voltage lines across the SRAM cell array from the front-side to the back-side through tapping structures, and fabricates butt contacts on the back-side to reduce IR drop and fabrication costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If functional density is increased and geometry size is decreased through scaling down, then production efficiency is improved and costs are lowered, but power dissipation increases
Solution Approach 1:
The patent implements a back-side contact architecture where word-lines are routed on the back-side of the substrate rather than the front-side, creating a three-dimensional interconnect structure. This dimensional separation allows front-side bit-lines to operate independently without interference, reducing capacitive coupling and power dissipation while maintaining high functional density on the front-side
2Productivity
If metal line density is increased to support higher functional density, then more circuits can be integrated, but resistance and capacitance in metal lines increase
Solution Approach 1:
By moving word-line routing to the back-side, the patent creates vertical separation between bit-lines and word-lines, reducing parasitic capacitance between intersecting lines. This dimensional reorganization maintains signal integrity even as metal line density increases to support higher functional density
Solution Approach 2:
The back-side substrate acts as an intermediary layer that carries word-lines away from the front-side circuitry. This intermediate structure reduces direct electromagnetic interference and capacitive coupling between bit-lines and word-lines, preserving signal integrity in high-density configurations
Data Source
AI summary
A method includes forming a static random access memory (SRAM) array comprising a plurality of SRAM cells, at least one of the SRAM cells comprising first and second pull-up transistors, first and second pull-down transistors, and first and second pass-gate transistors; forming a first front-side metal layer above the SRAM array, the first front-side metal layer comprising a first power supply voltage line and a bit-line, the first power supply voltage line electrically coupled to the first and second pull-up transistors, and the bit-line electrically coupled to the first pass-gate transistor; forming a back-side butt contact extending from a back-side of a gate structure of the first pull-up transistor to a back-side of a source/drain region of the second pull-up transistor from a cross sectional view.