SRAM Cell Backside Interconnect Layout for Low-Resistance Contacts
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Solution Overview
Problem
As integrated circuit technologies progress towards smaller technology nodes, the shrinkage in dimensions of SRAM cells presents challenges in reducing resistance (R) and capacitance (C) in contact structures, leading to low drive current and slow speed.
Innovation Solution
The implementation of both frontside and backside interconnects in SRAM devices, where sources of pull-down transistors are coupled to a backside ground rail through backside contacts, improves the beta and alpha ratios, reduces contact resistance, and provides additional electrical routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If contact structures are scaled down to reduce SRAM cell dimensions, then manufacturing cost decreases and production efficiency improves, but resistance and capacitance in contact structures increase, leading to low drive current and slow speed
Solution Approach 1:
The patent introduces backside contacts that extend the interconnect structure into the vertical dimension, allowing current to flow through multiple paths (frontside and backside) simultaneously. This dimensional expansion effectively reduces the electrical resistance and capacitance without requiring further lateral scaling, thereby maintaining drive current speed while supporting continued lateral scaling for improved productivity
2Area of moving object
If contact structures are scaled down, then SRAM cell area decreases, but resistance and capacitance increase, resulting in low drive current
Solution Approach 1:
By extending interconnects to the backside of the device, the patent creates additional current pathways that reduce electrical resistance. This allows smaller SRAM cell areas to maintain adequate drive current levels, as the vertical extension compensates for the reduced lateral dimensions
Solution Approach 2:
The patent merges frontside and backside interconnect structures to create parallel current paths. This combination of interconnect layers effectively reduces the total resistance and capacitance, enabling smaller cell areas to achieve sufficient drive current for proper operation
3Device complexity
If conventional single-sided interconnects are used, then device structure is simple, but contact resistance is high and additional routing space is required
Solution Approach 1:
The patent moves part of the interconnect function to the backside of the device, creating vertical current paths that bypass the limitations of planar routing. This reduces contact resistance by providing alternative current flow paths while the modular backside contact approach keeps the overall device complexity manageable
Data Source
AI summary
A semiconductor structure according to the present disclosure includes a first memory cell that includes a first pull-down transistor and a first pull-up transistor sharing a first gate structure extending along a first direction, a second pull-down transistor and a second pull-up transistor sharing a second gate structure extending along the first direction, a first pass-gate transistor having a third gate structure spaced apart but aligned with the second gate structure along the first direction, and a second pass-gate transistor having a fourth gate structure spaced apart but aligned with the first gate structure along the first direction, a frontside interconnect structure disposed over the first memory device, a backside interconnect structure disposed below the first memory device. A source of the second pull-down transistor is electrically coupled to the backside interconnect structure by way of a first backside contact via.