SRAM Gate-Source/Drain Backside Contact for Low-Leakage Connections
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Solution Overview
Problem
Existing gate-to-source/drain connections in semiconductor integrated circuits suffer from limited contact surfaces, leading to high contact resistance and current leakage, which can cause power consumption issues and circuit failure due to densely spaced features.
Innovation Solution
Implementing a backside butted contact configuration that electrically connects the gate structure and source/drain feature, increasing contact area and alleviating leakage and short issues by forming the contact under the source/drain feature.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a butted contact is formed over the source/drain feature to connect gate structure and source/drain feature, then electrical connection is achieved, but contact resistance increases and connection reliability deteriorates due to limited contact surface area
Solution Approach 1:
The contact feature is moved from a planar configuration (over the source/drain feature) to a vertical configuration (through the source/drain feature). This dimensional change allows the contact to access the bottom surface of the gate structure, creating multiple contact interfaces (top surface of source/drain feature + bottom surface of gate structure) and significantly increasing the effective contact area, thereby reducing contact resistance and improving connection reliability.
2Productivity
If device sizes are scaled down to increase functional density, then production efficiency improves and costs decrease, but contact surface area reduces leading to higher contact resistance
Solution Approach 1:
By transitioning from a planar contact arrangement to a vertical through-contact arrangement, the invention increases the contact area in the vertical dimension. This allows continued scaling of device sizes and functional density while maintaining adequate contact surface area through the vertical penetration of the contact feature through the source/drain feature to reach the gate structure bottom surface.
3Productivity
If butted contact is positioned close to neighboring conductive features to save space, then device density increases, but current leakage increases leading to higher power consumption
Solution Approach 1:
The harmful effect of current leakage is eliminated by extracting the leakage path from the system. The through-contact configuration with proper spacing from neighboring conductive features removes the leakage pathway that would exist in planar configurations, allowing dense packing without the harmful side effect of current leakage and associated power consumption.
4Reliability
If contact area between gate structure and source/drain feature is increased to reduce contact resistance, then connection reliability improves, but device area increases reducing functional density
Solution Approach 1:
The invention resolves the area conflict by moving the contact expansion from the horizontal plane to the vertical dimension. The through-contact structure increases contact area by penetrating vertically through the source/drain feature and contacting the gate structure bottom surface, rather than expanding horizontally. This maintains compact device footprint while achieving adequate contact area for reliable low-resistance connections.
Data Source
AI summary
An IC structure includes an SRAM cell. In an embodiment, the SRAM cell includes a channel region over a substrate, a source/drain feature coupled to the channel region, a gate structure intersecting the channel region, and a first contact feature electrically coupled to the source/drain feature and the gate structure. A portion of the first contact feature is disposed directly under the gate structure.