SRAM Gate-Source/Drain Backside Contact Layout for Leakage Control
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Solution Overview
Problem
Aggressive scaling down of IC dimensions leads to densely spaced source/drain contacts and gate structures, resulting in high contact resistance, current leakage, and increased power consumption due to limited contact surfaces and close proximity of conductive features, which can cause circuit failure.
Innovation Solution
The introduction of a backside butted contact configuration, where the butted contact is formed under the source/drain feature, increasing the contact area with the gate structure and source/drain feature, and allowing for design flexibility of metal lines by occupying space otherwise used by frontside butted contacts, thereby alleviating leakage and short issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional butted contact configuration is used for gate-to-source/drain connection, then device density can be maintained, but contact resistance increases and connection reliability deteriorates due to limited contact surfaces
Solution Approach 1:
The patent transitions from a planar contact configuration to a three-dimensional configuration by forming the contact structure that extends vertically to engage the sidewall of the gate structure. This vertical extension adds a new dimension to the contact interface, significantly increasing the contact surface area without occupying additional lateral space, thereby improving connection reliability while maintaining device density.
2Productivity
If butted contact is positioned close to neighboring conductive features to maintain compact layout, then device density improves, but current leakage increases and power consumption rises
Solution Approach 1:
The patent introduces a dielectric material as an intermediary substance between the butted contact structure and neighboring conductive features. This dielectric layer acts as an electrical insulator that prevents current leakage paths while allowing the contact to be positioned in a compact layout. The intermediary dielectric layer enables close spacing of conductive features without compromising electrical isolation, thus maintaining high device density while eliminating harmful leakage currents.
3Reliability
If contact area between butted contact and gate structure is increased to reduce contact resistance, then connection quality improves, but space for metal line routing is reduced
Solution Approach 1:
The patent resolves this contradiction by extending the contact structure vertically along the sidewall of the gate structure, utilizing the third dimension (vertical direction) to increase contact area. This vertical extension provides sufficient contact surface area for low contact resistance without consuming additional lateral space, thereby preserving design flexibility for metal line routing and interconnect layout.
Data Source
AI summary
An IC structure includes an SRAM cell. In an embodiment, the SRAM cell includes a channel region over a substrate, a source/drain feature coupled to the channel region, a gate structure intersecting the channel region, and a first contact feature electrically coupled to the source/drain feature and the gate structure. A portion of the first contact feature is disposed directly under the gate structure.